Non-volatile memory (NVM) and high-k and metal gate integration using gate-last methodology
View Patent ↗A method of making a semiconductor structure uses a substrate and includes a logic device in a logic region and a non-volatile memory (NVM) device in an NVM region. An NVM structure is formed in the NVM region. The NVM structure includes a control gate structure and a select gate structure. A protective layer is formed over the NVM structure. A gate dielectric layer is formed over the substrate in the logic region. The gate dielectric layer includes a high-k dielectric. A sacrificial gate is formed over the gate dielectric layer in the logic region. A first dielectric layer is formed around the sacrificial gate. Chemical mechanical polishing is performed on the NVM region and the logic region after forming the first dielectric layer. The sacrificial gate is replaced with a metal gate structure.
1. A method of making a semiconductor structure using a substrate, wherein the semiconductor structure comprises a logic device in a logic region and a non-volatile memory (NVM) device in an NVM region, comprising:
forming an NVM structure in the NVM region, wherein the NVM structure comprises a control gate structure and a select gate structure;
forming a protective layer over the NVM structure;
forming a gate dielectric layer over the substrate in the logic region after forming the protective layer over the NVM structure, wherein the gate dielectric layer comprises a high-k dielectric;
forming a sacrificial gate over the gate dielectric layer in the logic region;
forming a first dielectric layer around the sacrificial gate; and
performing chemical mechanical polishing on the NVM region and the logic region after forming the first dielectric layer; and
replacing the sacrificial gate with a metal gate structure.
2. The method of claim 1 wherein the forming the NVM structure is further characterized by the select gate having a top surface and the control gate structure having an upper portion overlapping a portion of the top surface of the select gate.
3. The method of claim 2 , wherein performing chemical mechanical polishing includes depositing a layer of polysilicon over the top of the control gate and then removing the upper portion of the control gate that overlaps the portion of the top surface of the select gate.
4. The method of claim 3 , further comprising performing the source/drain implants in the NVM region and the logic region prior to forming the first dielectric layer.
5. The method of claim 4 , further comprising forming a first sidewall spacer around the sacrificial gate after forming the first sidewall spacer and before forming the first dielectric layer.
6. The method of claim 5 , wherein the replacing the sacrificial gate comprises:
removing the sacrificial gate to leave an opening over the gate dielectric layer; and
forming a work function metal in the opening.
7. The method of claim 6 , wherein the replacing the sacrificial gate further comprises forming a metal gate on the work function metal.
8. The method of claim 1 wherein the forming the NVM structure is further characterized by forming a capping layer on the top surface of the select gate.
9. The method of claim 8 , wherein the forming the capping layer is characterized by the capping layer comprising nitride.
10. The method of claim 9 , wherein the performing the chemical mechanical polishing is further characterized as leaving at least a portion of the capping layer over the select gate structure.
11. The method of claim 1 , wherein the protective layer comprises a first oxide layer, a nitride layer on the first oxide layer, and a second oxide layer on the nitride layer.
12. The method of claim 11 , further comprising:
removing the second oxide layer and the nitride layer; and
anisotropically etching the first oxide layer to form a sidewall spacer around the select gate structure and the control gate structure.
13. The method of claim 12 wherein the forming the NVM structure is further characterized by the control gate structure and the select gate structure comprising polysilicon.
14. A method of making a semiconductor structure using a substrate, wherein the semiconductor structure comprises a logic device in a logic region and a non-volatile memory (NVM) device in an NVM region, comprising:
forming an NVM structure in the NVM region, wherein the NVM structure comprises a control gate structure and a select gate structure in which the control gate structure has an upper portion extending over a portion of a top surface of the select gate structure;
forming a replacement gate structure in the logic region having a sacrificial gate;
performing chemical mechanical polishing on the logic region and the NVM region which removes the upper portion of the control gate structure; and
replacing the sacrificial gate with a metal gate structure.
15. The method of claim 14 , wherein the forming the replacement gate structure comprises forming a gate dielectric comprising a high-k dielectric.
16. The method of claim 15 , wherein the forming the replacement gate structure:
is further characterized by the sacrificial gate comprising polysilicon; and
further comprises forming a barrier layer on the gate dielectric.
17. The method of claim 16 wherein the replacing the sacrificial gate is further characterized by the metal gate structure comprising:
a work function metal on the barrier layer; and
a metal gate on the work function metal.
18. The method of claim 14 further comprising forming a protection layer over the NVM region after forming the NVM structure and before forming the replacement gate structure.
19. The method of claim 18 further comprising:
forming a capping layer over the select gate prior to forming the protection layer; and
removing a portion of the capping layer during the performing the chemical mechanical polishing.
20. A method of making a semiconductor structure using a substrate, wherein the semiconductor structure comprises a logic device in a logic region and a non-volatile memory (NVM) device in an NVM region, comprising:
forming an NVM structure in the NVM region, wherein the NVM structure comprises a control gate structure and a select gate structure in which the control gate structure has an upper portion extending over a portion of a top surface of the select gate structure and the select gate structure has a nitride capping layer on its top surface;
forming a protection layer over the NVM region
forming a replacement gate structure in the logic region having a high-k dielectric, a barrier layer on the high-k dielectric, and a sacrificial gate;
performing chemical mechanical polishing on the logic region and the NVM region which removes the upper portion of the control gate structure and leaves a portion of the nitride capping layer on the top surface of the select gate structure; and
replacing the sacrificial gate with a work function metal on the barrier layer and a metal gate on the barrier layer.