Split gate non-volatile memory cell
View Patent ↗A method of making a semiconductor structure uses a substrate having a background doping of a first type. A gate structure has a gate dielectric on the substrate and a select gate layer on the gate dielectric. Implanting is performed into a first portion of the substrate adjacent to a first end with dopants of a second type. The implanting is prior to any dopants being implanted into the background doping of the first portion which becomes a first doped region of the second type. An NVM gate structure has a select gate, a storage layer having a first portion over the first doped region, and a control gate over the storage layer. Implanting at a non-vertical angle with dopants of the first type forms a deep doped region under the select gate. Implanting with dopants of the second type forms a source/drain extension.
1. A method of making a semiconductor structure using a substrate having a background doping of a first conductivity type, comprising:
forming a gate structure comprising a gate dielectric on the substrate and a select gate layer on the gate dielectric, wherein the gate layer has a first end;
implanting a first portion of the substrate adjacent to the first end with dopants of a second conductivity type using the first end as a mask, wherein the implanting is prior to any dopants being implanted into the background doping of the first portion and wherein the first portion becomes a first doped region of the second conductivity type;
forming a non-volatile memory gate structure comprising a select gate of the select gate layer, a storage layer having a first portion over the first doped region, and a control gate over the storage layer, wherein the select gate has a first side as the first end and a second side opposite the first side, wherein the storage layer has a second portion between the first side of the select gate and a first side of the control gate;
implanting at a non-vertical angle with dopants of the first conductivity type to form a deep doped region under substantially all of the select gate; and
implanting with dopants of the second conductivity type to from a source/drain extension in the substrate substantially aligned with the second side of the select gate.
2. The method of claim 1 , wherein the control gate has a second side opposite the first side of the control gate, further comprising:
forming a sidewall spacer along the second side of the select gate and the second side of the control gate; and
implanting with dopants of the second conductivity type using the sidewall spacer as a mask to form a deep source/drain region in the substrate substantially aligned to the second side of the select gate and a deep source/drain region in the substrate substantially aligned to the second side of the control gate.
3. The method of claim 2 further comprising:
forming a silicide layer on deep source/drain region and a silicide layer on the control gate.
4. The method of claim 1 , wherein the storage layer comprises nanocrystals.
5. The method of claim 1 wherein the gate structure further comprises a dielectric layer on the select gate layer.
6. The method of claim 1 , wherein the implanting at a non-vertical angle is further characterized as using the control gate as a mask.
7. The method of claim 1 , wherein the implanting at a non-vertical angle is further characterized as using a layer of patterned photoresist as a mask.
8. The method of claim 1 , wherein the dopants of the second conductivity type implanted during the implanting the first portion are the only dopants in addition to the dopants of the background doping in all of the substrate.
9. The method of claim 1 , wherein the implanting at the non-vertical angle is further characterized as implanting a dopant comprising one of a group consisting of boron difluoride and boron.
10. The method of claim 1 , wherein the select gate is formed by etching the select gate layer to form the select gate with the second side.
11. The method of claim 1 , wherein the select gate layer has the second side and wherein the implanting the first portion of the substrate is further characterized as implanting a second portion of the substrate adjacent to the second side of the select gate layer.
12. The method of claim 1 , wherein the implanting the first portion of the substrate is further characterized as being non-vertical.
13. The method of claim 1 , wherein the forming the non-volatile memory gate structure is further characterized by the storage layer extending over a portion of the select gate and the control gate extending over the storage layer where the storage layer extends over the portion of the select gate.
14. A method of making split gate memory cell using a substrate having a background doping of a first conductivity type, comprising:
forming a select gate structure over a gate dielectric, wherein the select gate structure has a first end;
performing a shallow, non-vertical implant using the select gate structure as a mask to obtain a doped region in a first portion in the substrate adjacent to the first end, wherein the non-vertical implant is the only implant into the background doping of the first portion;
forming a non-volatile gate structure using the select gate structure in forming a select gate transistor portion of the split gate memory cell, wherein the non-volatile gate structure includes a control gate structure over the doped region with a storage layer between the control gate structure and the doped region for use in a control gate transistor portion of the split gate memory cell; and
then performing a deep, non-vertical implant of dopants of the first conductivity type into a channel region of the select gate transistor portion as a threshold adjust of the select gate transistor portion, wherein the deep non-vertical implant is deeper than the shallow, non-vertical implant.
15. A method of making a split gate non-volatile memory cell using a substrate having a background doping of a first conductivity type, comprising:
forming a gate dielectric on the substrate;
forming a select gate on the gate dielectric having a first side and a second side;
forming a storage layer that is along the first side of the select gate and over a first portion of the substrate adjacent to the first side of the select gate; and
forming a control gate, which has a first portion over the storage layer where the storage layer is over the first portion of the substrate, wherein the control gate has a first side adjacent to the storage layer where the storage layer is along the first side of the select gate, and wherein the control gate has a second side opposite the first side of the control gate;
implanting a first doped region in the substrate under the first portion of the control gate, wherein the doped region has dopants of a second conductivity type sufficient for the first doped region to be of the second conductivity type and all dopants of the first conductivity type are only from the background doping of the substrate;
implanting a second doped region of the first conductivity type having a greater concentration than the background doping in the substrate under the select gate;
implanting a third doped region of the second conductivity type in the substrate substantially aligned to the second side of the select gate; and
implanting a fourth doped region of the second conductivity type in the substrate adjacent to the first doped region.
16. The method of claim 15 , wherein the storage layer extends over a portion of the select gate and the control gate extends over the storage layer where the storage layer extends over the select gate.
17. The method of claim 15 , wherein:
the second doped region extends from a top surface of substrate to a first depth and functions as a threshold adjust for a select gate transistor portion of the split gate memory cell; and
the first doped region extends from a surface of the substrate to a second depth and functions as an only threshold adjust to the background doping for a control gate portion of the split gate memory cell, wherein the first depth is greater than the second depth.
18. The method of claim 15 , further comprising a sidewall spacer on the second side of the select gate and the second side of the control gate.
19. The method of claim 15 , wherein the first doped region forms a PN junction with the second doped region, wherein the PN junction is at the top surface of the substrate and under the select gate.
20. The method of claim 15 , wherein the storage layer comprises nanocrystals.