Hybrid lead frame and ball grid array package
View Patent ↗A semiconductor device includes a first substrate having opposing first and second main surfaces, a first die disposed on the first main surface of the first substrate, a first bond wire coupled to the first die, a first packaging material encapsulating the first die and the first bond wire, and a lead frame disposed on the first main surface of the first substrate and in electrical communication with the first bond wire. At least a portion of the lead frame extends outside of the packaging material. A top package includes first and second main surfaces and an electrical contact on the second main surface. The electrical contact is electrically connected to the lead frame and connects the top package to either the first die and/or external circuitry.
1. A semiconductor device comprising:
a first substrate having opposing first and second main surfaces;
a first die disposed on the first main surface of the first substrate;
a first bond wire coupled to the first die;
a first packaging material encapsulating the first die and the first bond wire;
a lead frame disposed on the first main surface of the first substrate and in electrical communication with the first bond wire, at least a portion of the lead frame extending outside of the first packaging material, wherein the lead frame is U-shaped and comprises a first portion lying along the first main surface of the first substrate, an adjacent second portion extending vertically away from the first main surface of the first substrate, and a third portion extending parallel to and spaced from the first main surface of the first substrate; and
a top package having first and second main surfaces and an electrical contact on the second main surface, the electrical contact being electrically connected to the third portion of the lead frame.
2. The semiconductor device of claim 1 , wherein the first substrate includes an electrical trace on the first main surface thereof, the first bond wire and the lead frame being coupled to the electrical trace.
3. The semiconductor device of claim 1 , wherein the lead frame is coupled to the electrical contact of the top package by a solder ball.
4. The semiconductor device of claim 1 , wherein the top package is a wafer-level package.
5. The semiconductor device of claim 1 , wherein the top package comprises
a second substrate having opposing first and second main surfaces, the electrical contact being disposed on the second main surface of the second substrate;
a second die disposed on the first main surface of the second substrate;
a second bond wire coupled to the second die and in electrical communication with the electrical contact; and
a second packaging material encapsulating the second die and the second bond wire.
6. The semiconductor device of claim 1 , wherein the lead frame is soldered directly to the electrical contact of the top package.
7. The semiconductor device of claim 1 , wherein the first wire bond is directly coupled to the lead frame.
8. The semiconductor device of claim 1 , wherein the lead frame is located entirely outside of the packaging material.
9. The semiconductor device of claim 1 , wherein the lead frame is attached to the first main surface of the first substrate by an adhesive.
10. The semiconductor device of claim 1 , further comprising a second die stacked on the first die; and
a second bond wire coupled to the second die and in electrical communication with the lead frame.