Semiconductor device with self-biased isolation
View Patent ↗A method of fabricating a reduced surface field (RESURF) transistor includes forming a first well in a substrate, the first well having a first conductivity type, doping a RESURF region of the first well to have a second conductivity type, doping a portion of the first well to form a drain region of the RESURF transistor, the drain region having the first conductivity type, and forming a second well in the substrate, the second well having the second conductivity type. A plug region is formed in the substrate, the plug region extending to the RESURF region.
1. A method of fabricating a reduced surface field (RESURF) transistor, the method comprising:
forming a first well in a substrate, the first well having a first conductivity type;
doping a RESURF region of the first well to have a second conductivity type;
doping a portion of the first well to form a drain region of the RESURF transistor, the drain region having the first conductivity type; and
forming a second well in the substrate, the second well having the second conductivity type;
wherein a plug region is formed in the substrate, the plug region extending to the RESURF region.
2. The method of claim 1 , further comprising:
forming a device isolation well surrounding an active area of the RESURF transistor and having the first conductivity type; and
electrically tying the device isolation well to the plug region.
3. The method of claim 2 , wherein electrically tying the device isolation well to the plug region comprises depositing a metal layer.
4. The method of claim 3 , wherein:
the plug region is one of a plurality of plug regions spaced from one another and that extend to the RESURF region; and
the metal layer comprises a plurality of fingers, each finger being connected to a respective one of the plurality of plug regions.
5. The method of claim 2 , wherein an upper surface of the RESURF region and the device isolation well are electrically linked via the plug region.
6. The method of claim 1 , further comprising:
doping an original substrate of the substrate to form an isolation layer that extends across an active area of the RESURF transistor; and
growing an epitaxial layer on the original substrate to form the substrate such that the isolation layer is configured as a buried isolation layer;
wherein the buried isolation layer is adjacent and electrically coupled to the device isolation well.
7. The method of claim 6 , wherein the first and second wells are formed in the epitaxial layer.
8. The method of claim 1 , wherein the second well is configured as a body region of the RESURF transistor.
9. The method of claim 1 , wherein the first well is configured as a drift region of the RESURF transistor.
10. The method of claim 1 , wherein the plug region is formed while the second well is formed.
11. The method of claim 1 , wherein the plug region extends from a surface of the substrate to the RESURF region.
12. A method of fabricating a transistor, the method comprising:
forming a well in a substrate, the well having a first conductivity type;
doping a first region of the well to have a second conductivity type, the first region being disposed between a buried isolation layer in the substrate and a second region of the well, the buried isolation layer having the first conductivity type;
doping a third region of the well to form a drain of the transistor, the third region having the first conductivity type; and
implanting dopant of the second conductivity type in the substrate to form a body region of the transistor and a plug region, the plug region extending from a surface of the substrate to the first region.
13. The method of claim 12 , further comprising:
forming a device isolation well surrounding an active area of the transistor and having the first conductivity type; and
electrically tying the device isolation well to the plug region.
14. The method of claim 13 , wherein electrically tying the device isolation well to the plug region comprises depositing a metal layer.
15. The method of claim 14 , wherein:
the plug region is one of a plurality of plug regions spaced from one another, each plug region being disposed between respective portions of the drain and extending from the surface to the first region; and
the metal layer comprises a plurality of fingers, each finger being connected to a respective one of the plurality of plug regions.
16. The method of claim 13 , wherein an upper surface of the first region and the device isolation well are electrically linked via the plug region.
17. The method of claim 12 , further comprising:
doping an original substrate of the substrate to form a doped layer that extends across an active area of the transistor; and
growing an epitaxial layer on the original substrate to form the substrate such that the doped layer forms the buried isolation layer;
wherein the buried isolation layer is adjacent and electrically coupled to the device isolation well.
18. The method of claim 17 , wherein the well and the body region are formed in the epitaxial layer.
19. A method of fabricating a transistor, the method comprising:
forming a well in a substrate, the well having a first conductivity type;
doping a first region of the well to have a second conductivity type, the first region being disposed between a buried isolation layer in the substrate and a second region of the well, the second region being disposed in a drift space of the transistor, the buried isolation layer having the first conductivity type;
doping a third region of the well to form a drain of the transistor, the third region having the first conductivity type; and
implanting dopant of the second conductivity type in the substrate to form a body region of the transistor and a plurality of fourth regions spaced from one another, each fourth region being disposed between respective portions of the drain and extending through the well from a surface of the substrate to the first region.
20. The method of claim 19 , further comprising:
doping an original substrate of the substrate to form a doped layer having the first conductivity type and that extends across an active area of the transistor; and
growing an epitaxial layer on the original substrate to form the substrate such that the doped layer forms the buried isolation layer;
forming a device isolation well surrounding the active area of the transistor and having the first conductivity type; and
electrically tying the device isolation well to the plurality of fourth regions.