Non-volatile memory (NVM) and high-K and metal gate integration using gate-last methodology
A method of making a semiconductor structure includes forming a select gate over a substrate in an NVM region and a first protection layer over a logic region. A control gate and a storage layer are formed over the substrate in the NVM region. The control gate has a top surface below a top surface of the select gate. The charge storage layer is under the control gate, along adjacent sidewalls of the select gate and control gate, and is partially over the top surface of the select gate. A second protection layer is formed over the NVM portion and the logic portion. The first and second protection layers are removed from the logic region. A portion of the second protection layer is left over the control gate and the select gate. A gate structure, formed over the logic region, has a high k dielectric and a metal gate.
1. A method of making a semiconductor structure using a substrate having a non-volatile memory (NVM) portion and a logic portion, comprising:
forming a select gate over the substrate in the NVM portion and a first protection layer over the logic portion;
forming a control gate and a charge storage layer over the substrate in the NVM portion, wherein a top surface of the control gate is lower than a top surface of the select gate and the charge storage layer is under the control gate, along adjacent sidewalls of the select gate and control gate, is partially over the top surface of the select gate;
forming a second protection layer over the NVM portion and the logic portion;
removing the second protection layer and the first protection layer from the logic portion leaving a portion of the second protection layer over the control gate and the select gate;
forming a sacrificial gate stack over the logic portion comprising a gate dielectric of high k material and a sacrificial gate over the gate dielectric;
forming a dielectric around the sacrificial gate;
removing the sacrificial gate to leave an opening in the dielectric layer;
forming a work function metal over the gate dielectric in the opening; and
forming a metal gate over the work function metal in the opening.
2. The method of claim 1 , wherein the forming the control gate and the charge storage layer comprises:
forming a dielectric layer over the NVM region;
forming an opening in the dielectric layer adjacent to the select gate;
forming the charge storage layer in the opening in the dielectric layer partially filling the opening in the dielectric layer; and
forming the control gate in the opening in the dielectric layer over the charge storage layer; and
removing the dielectric layer.
3. The method of claim 2 , wherein the forming the control gate in the opening in the dielectric layer over the charge storage layer is further characterized by depositing a layer of polysilicon and etching the polysilicon layer.
4. The method of claim 3 , wherein the forming the control gate and the charge storage layer is further characterized by the charge storage layer comprising nanocrystals.
5. The method of claim 1 , wherein the forming the control gate and the charge storage layer comprises:
forming the charge storage layer over the NVM region including over the select gate;
forming a polysilicon layer over the charge storage layer;
etching the polysilicon layer so that a resulting top surface of the polysilicon layer is below the top surface of the select gate; and
patterning the polysilicon layer and the charge storage layer to leave a first portion of the charge storage layer adjacent to the select gate and a second portion extending laterally from the select gate and a portion of the polysilicon layer as the control gate over the second portion of the charge storage layer and adjacent to the first portion of the select gate.
6. The method of claim 1 , further comprising:
depositing a conformal layer over NVM portion and the logic portion; and
etching the conformal layer to leave a first sidewall spacer around the logic gate and a second sidewall spacer around the control and select gate.
7. The method of claim 6 , further comprising performing an implant into the substrate using the first and second sidewall spacers as masks for the implant.
8. The method of claim 7 , wherein the forming the second protection layer comprises forming a first oxide layer, a nitride layer on the first oxide layer, and a second oxide layer on the nitride layer.
9. The method of claim 1 , wherein the step of forming the select gate and the protection layer comprises:
growing thermal oxide on the substrate in NVM region;
depositing a layer of polysilicon over the thermal oxide;
patterning the layer of polysilicon to leave a portion of the layer of polysilicon as the select gate in the NVM region and the layer of polysilicon in the logic region as the protection layer.
10. The method of claim 9 , further comprising forming a capping layer on the layer of polysilicon.
11. The method of claim 10 , wherein the patterning is further characterized by patterning the capping layer with a same pattern as the layer of polysilicon.
12. The method of claim 1 , wherein the second protection layer comprises a first layer of oxide, a layer of nitride, and a second layer of oxide on the layer of nitride.
13. The method of claim 1 , wherein the forming the charge storage layer and the control gate further comprises etching the charge storage layer to leave the top surface of the select gate partially covered with the charge storage layer.
14. A method of making a semiconductor structure using a substrate having a non-volatile memory (NVM) region and a logic region, comprising:
growing thermal oxide on the substrate in the NVM portion;
forming a select gate in the NVM portion on the thermal oxide;
counterdoping the substrate in the NVM portion adjacent to the select gate;
forming a control gate and a charge storage layer over the substrate in the NVM portion, wherein a top surface of the control gate is below a top surface of the select gate and the charge storage layer is under the control gate, along adjacent sidewalls of the select gate and control gate, is partially over the top surface of the select gate;
forming a protective layer over the NVM portion and the logic portion;
removing the protective layer from the logic portion;
forming a gate structure in the logic portion comprising a high k dielectric as a gate dielectric and a sacrificial gate over the gate dielectric;
forming a layer of dielectric material around the gate structure;
removing the sacrificial gate to leave an opening in the layer of dielectric material; and
forming a work function metal in the opening.
15. The method of claim 14 , wherein the protective layer comprises a three layer stack comprising oxide, nitride, and oxide.
16. The method of claim 14 , wherein the forming the control gate and the charge storage layer comprises:
forming a dielectric layer over the NVM region;
forming an opening in the dielectric layer adjacent to the select gate;
forming the charge storage layer in the opening in the dielectric layer partially filling the opening in the dielectric layer;
forming the control gate in the opening in the dielectric layer over the charge storage layer; and
removing the dielectric layer.
17. The method of claim 1 , wherein the forming the control gate and the charge storage layer comprises:
forming the charge storage layer over the NVM region including over the select gate;
forming a polysilicon layer over the charge storage layer; and
etching back the polysilicon layer so that a resulting top surface of the polysilicon layer is below the top surface of the select gate; patterning the polysilicon layer and the charge storage layer to leave a first portion of the charge storage layer adjacent to the select gate and a second portion extending laterally from the select gate and a portion of the polysilicon layer as the control gate over the second portion of the charge storage layer and adjacent to the first portion of the select gate.
18. The method of claim 14 , wherein the forming the layer of dielectric material comprises forming a first sidewall spacer around the gate stack and forming an interlayer dielectric around the first sidewall spacer.