Universal SPI (serial peripheral interface)
View Patent ↗A Universal SPI Interface is provided that is compatible, without the need for additional interface logic or software, with the SPI bus, existing DSA and other serial busses similar to (but not directly compatible with) the SPI bus, and parallel busses requiring compatibility with 74xx164-type signaling. In an additional aspect, a reduced-pincount Universal SPI Interface is provided that provides the same universal interface, but using fewer external output pins. The Universal SPI Interface includes multiple latches, buffers, and in an alternative embodiment, a multiplexer, configured together such that a Universal SPI interface is provided that can be readily reconfigured using only input signals to provide compatibility across multiple bus interfaces.
1. A universal serial bus interface device comprising:
a first latch comprising a first data input, a clock input, a latch enable input, and a first data output; the first latch configured, when an enable signal having a particular logic value is present at the latch enable input, to latch data present on the first data input and provide that data on the first data output responsive to a clock transition of a first type of a signal provided at the clock input, wherein transitioning the enable signal to have a value other than the particular logic value does not change the data stored at the first latch;
a second latch comprising a clock input, a latch enable input electrically coupled to the latch enable input of the first latch, a second data output, and a second data input electrically coupled to the first data output of the first latch, the second latch configured, when an enable signal having the particular logic value is present at the latch enable input, to latch data present on the second data input and provide that data on the second data output responsive to a clock transition of the first type of a signal provided at the clock input, wherein transitioning the enable signal to have a value other than the particular logic value does not change the data stored at the second latch; and
a third latch comprising a clock input, a third data output, and a third data input electrically coupled to the second data output of the second latch, the third latch configured to latch data present on the third data input and provide that data on the third data output responsive to a clock transition of a second type of a signal provided at the clock input, wherein the data provided on the third data output is delayed in time relative to the data provided on the second data output of the second latch, and wherein the clock inputs of the first latch, second latch, and third latch are electrically coupled to share the same clock signal.
2. A universal serial bus interface device as claimed in claim 1 further comprising a first buffer comprising a first buffer data output, a first buffer control input, and a first buffer data input electrically coupled to the second data output of the second latch, wherein the first buffer is configured to provide data present on the second data output of the second latch at the first buffer data output responsive to an asserted signal present at the first buffer control input having the particular logic value.
3. A universal serial bus interface device as claimed in claim 2 further comprising a second buffer comprising a second buffer data output, a second buffer control input, and a second buffer data input electrically coupled to the third data output of the third latch, wherein the second buffer is configured to provide data present on the third data output of the third latch at the third buffer data output responsive to an asserted signal present at the second buffer control input having the particular logic value.
4. A universal serial bus interface device as claimed in claim 1 further comprising a second buffer comprising a second buffer data output, a second buffer control input, and a second buffer data input electrically coupled to the third data output of the third latch, wherein the second buffer is configured to provide data present on the third data output of the third latch at the third buffer data output responsive to an asserted signal present at the second buffer control input having the particular logic value.
5. A universal serial bus interface device as claimed in claim 1 further comprising a fourth shadow latch comprising a clock input, a fourth data output, and a fourth data input electrically coupled to the first data output of the first latch, the fourth latch configured to latch data present on the fourth data input and provide that data on the fourth data output responsive to a signal provided at the clock input of the fourth shadow latch.
6. A universal serial bus interface device as claimed in claim 1 further comprising a multiplexer having a select input, a first multiplexer input electrically coupled to the second data output of the second latch, a second multiplexer input electrically coupled to the third data output of the third latch, and a multiplexer output, wherein the multiplexer is configured to provide at the multiplexer output one of data present at the first multiplexer input and data present at the second multiplexer input responsive to a signal present at the select input.
7. A universal serial bus interface device as claimed in claim 5 further comprising a fifth shadow latch comprising a clock input electrically coupled to the clock input of the fourth shadow latch, a fifth data output, and a fifth data input electrically coupled to the second data output of the second latch, the fifth latch configured to latch data present on the fifth data input and provide that data on the fifth data output responsive to a signal provided at the clock input.
8. A universal serial bus interface device as claimed in claim 3 further comprising:
a fourth shadow latch comprising a clock input, a fourth data output, and a fourth data input electrically coupled to the first data output of the first latch, the fourth latch configured to latch data present on the fourth data input and provide that data on the fourth data output responsive to a signal provided at the clock input; and
a fifth shadow latch comprising a clock input electrically coupled to the clock input of the fourth shadow latch, a fifth data output, and a fifth data input electrically coupled to the second data output of the second latch, the fifth latch configured to latch data present on the fifth data input and provide that data on the fifth data output responsive to a signal provided at the clock input.
9. A universal serial bus interface device as claimed in claim 3 further comprising a SPI bus having SSB, SCLK, SDI and SDO signals, wherein the latch enable inputs of the first and second latches, and buffer control inputs of the first and second buffers are electrically coupled together and to the SSB signal of the SPI bus, wherein the clock signal of the first latch, second latch, and third latch are electrically coupled together and to the SCLK signal of the SPI bus, wherein the first data input of the first latch is electrically coupled to the SDI signal of the SPI bus, and wherein the second buffer output is electrically coupled to the SDO signal of the SPI bus.
10. A universal serial bus interface device as claimed in claim 3 further comprising a serial bus having SDI, SCLK, and LE signals, wherein the latch enable inputs of the first and second latches, and buffer control inputs of the first and second buffers are electrically coupled together and to ground, wherein ground is the particular logic value, wherein the clock signals of the first latch, second latch, and third latch are electrically coupled together and to the SCLK signal of the serial bus, wherein the first data input of the first latch is electrically coupled to the SDI signal of the serial bus, and wherein at least one of the first and second buffer outputs are electrically coupled to the SDO signal of the serial bus.
11. A universal serial bus interface device as claimed in claim 3 further comprising a serial bus having SDI, SCLK, and LE signals, wherein the buffer control inputs of the first and second buffers are electrically coupled to ground, wherein the latch enable inputs of the first and second latches, and clock inputs of the shadow latches are electrically coupled together and to the LE signal of the serial bus, wherein the clock signals of the first latch, second latch, and third latch are electrically coupled together and to the SCLK signal of the serial bus, wherein the first data input of the first latch is electrically coupled to the SDI signal of the serial bus, wherein at least one of the first and second buffer outputs are electrically coupled to the SDO signal of the serial bus, and wherein the LE signal is held in a logic high state except when new data is being provided to the universal serial bus interface device at the data input of the first latch.
12. A universal serial bus interface device as claimed in claim 8 further comprising a parallel bus, the universal serial bus interface having SDI, SCLK, and LE signals, wherein the latch enable inputs of the first and second latches, and buffer control inputs of the first and second buffers are electrically coupled together and to ground, wherein the clock inputs of the shadow latches are electrically coupled together and to the LE signal, wherein the clock signals of the first latch, second latch, and third latch are electrically coupled together and to the SCLK signal, wherein the first data input of the first latch is electrically coupled to the SDI signal, and wherein at least one of the first and second shadow latch data outputs are electrically coupled to the parallel bus.
13. A universal serial bus interface device as claimed in claim 8 further comprising a parallel bus, the universal serial bus having having SDI, SCLK, and LE signals, wherein the buffer control inputs of the first and second buffers are electrically coupled to ground, wherein the latch enable inputs of the first and second latches, and clock inputs of the shadow latches are electrically coupled together and to the LE signal, wherein the clock signals of the first latch, second latch, and third latch are electrically coupled together and to the SCLK signal, wherein the first data input of the first latch is electrically coupled to the SDI signal, wherein at least one of the first and second shadow latch data outputs are electrically coupled to the parallel bus, and wherein the LE signal is held in a logic high state except when new data is being provided to the universal serial bus interface device at the data input of the first latch.
14. A universal serial bus interface device as claimed in claim 6 further comprising a first buffer comprising a first buffer data output, a first buffer control input, and a first buffer data input electrically coupled to the multiplexer output, wherein the first buffer is configured to provide data present on the multiplexer output at the first buffer data output responsive to a signal present at the first buffer control input.
15. A universal serial bus interface device as claimed in claim 6 further comprising:
a fourth shadow latch comprising a clock input, a fourth data output, and a fourth data input electrically coupled to the first data output of the first latch, the fourth latch configured to latch data present on the fourth data input and provide that data on the fourth data output responsive to a signal provided at the clock input; and
a fifth shadow latch comprising a clock input electrically coupled to the clock input of the fourth shadow latch, a fifth data output, and a fifth data input electrically coupled to the second data output of the second latch, the fifth latch configured to latch data present on the fifth data input and provide that data on the fifth data output responsive to a signal provided at the clock input.
16. A universal serial bus interface device as claimed in claim 14 further comprising:
a fourth shadow latch comprising a clock input, a fourth data output, and a fourth data input electrically coupled to the first data output of the first latch, the fourth latch configured to latch data present on the fourth data input and provide that data on the fourth data output responsive to a signal provided at the clock input; and
a fifth shadow latch comprising a clock input electrically coupled to the clock input of the fourth shadow latch, a fifth data output, and a fifth data input electrically coupled to the second data output of the second latch, the fifth latch configured to latch data present on the fifth data input and provide that data on the fifth data output responsive to a signal provided at the clock input.