IP Library Patent Application 14029766
Patent Application
App. No. 14/029,766

SEMICONDUCTOR DEVICE AND LEAD FRAME WITH INTERPOSER

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Quick Facts
Patent No.
US None
App. No.
14/029,766
Abstract

A semiconductor device includes a lead frame having a flag and leads surrounding the flag. The flag includes a first die attach area and an interposer area. An insulated layer with at least one conductive trace is formed on the interposer area.

Claims (42)

1 . A semiconductor device, comprising:

a lead frame having a flag and a plurality of leads surrounding the flag, wherein the flag includes a first die attach area and an interposer area; and

an insulated layer plated with at least one conductive trace formed on the interposer area.

2 . The semiconductor device of claim 1 , further comprising:

a first die attached on the first die attach area;

a first bond wire electrically connecting the first die to a first end of the conductive trace; and

a second bond wire electrically connecting a second end of the conductive trace to a lead of the lead frame.

3 . The semiconductor device of claim 1 , further comprising:

a first die attached on the first die attach area;

a second die attached on a second die attach area of the lead frame;

a first bond wire electrically connecting the first die to a first end of the conductive trace; and

a second bond wire electrically connecting the second die to a second end of the conductive trace.

4 . The semiconductor device of claim 1 , wherein the insulated layer is glass, ceramic or polymer based material.

5 . The semiconductor device of claim 1 , wherein the conductive trace is a copper trace.

6 . The semiconductor device of claim 1 , further comprising a finishing layer plated on a top surface of the conductive trace for wire bonding.

7 . The semiconductor device of claim 1 , wherein the insulated layer has an L-shape, and the conductive trace is arranged along with the L-shape.

8 . The semiconductor device of claim 1 , wherein the insulated layer has a ring shape that allows a plurality of conductive traces arranged around a center of the ring shape.

9 . The semiconductor device of claim 1 , wherein the insulated layer is plated with a plurality of conductive traces, wherein each of the plurality of conductive traces has at least one contact element, wherein the contact elements of the plurality of conductive traces are arranged in a zigzag row.

10 . A lead frame, comprising:

a flag having a first die attach area and an interposer area;

a plurality of leads surrounding the flag; and

an insulated layer plated with at least one conductive trace formed on the interposer area.

11 . The lead frame of claim 10 , wherein the insulated layer is glass, ceramic or polymer based material.

12 . The lead frame of claim 10 , further comprising a silver layer plated on an upper surface of the conductive trace.

13 . The lead frame of claim 10 , wherein the insulated layer has an L-shape, and the conductive trace is arranged along with the L-shape.

14 . The lead frame of claim 10 , wherein the insulated layer has a ring shape that allows a plurality of conductive traces arranged around a center of the ring shape.

15 . The lead frame of claim 10 , wherein the insulated layer is plated with a plurality of conductive traces, wherein each of the plurality of conductive traces has at least one contact element, wherein the contact elements of the plurality of conductive traces are arranged in a zigzag row.

16 . A method for assembling a semiconductor device, the method comprising:

providing a lead frame having a flag and a plurality of leads surrounding the flag, wherein the flag includes a first die attach area and an interposer area;

forming an insulated layer on the interposer area; and

plating at least one conductive trace on the insulated layer.

17 . The method of claim 16 , further comprising:

attaching a first die on the first die attach area;

electrically connecting the first die to a first end of the conductive trace with a first bond wire; and

electrically connecting a second end of the conductive trace to a lead of the plurality of leads with a second bond wire.

18 . The method of claim 16 , further comprising:

attaching a first die on the first die attach area;

attaching a second die on a second die attach area of the flag;

electrically connecting the first die to a first end of the conductive trace with a first bond wire; and

electrically connecting the second die to a second end of the conductive trace with a second bond wire.

19 . The method of claim 16 , wherein the insulated layer is formed by a screen print or photo mask process.

20 . The method of claim 16 , further comprising plating a finishing layer on a top surface of the conductive trace for wire bonding.

Assignments (14)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PCT NUMBERS IB2013000664, US2013051970, US201305935 PREVIOUSLY RECORDED AT REEL: 037444 FRAME: 0787. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Oct 17, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 040450/0715 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0787 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0874 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 13, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 031627/0158 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 13, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031627/0201 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2013
From: YAP, JIA LIN; AU, YIN KHENG
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 031226/0538 →