State retention power gated cell
View Patent ↗A state retention power gated (SRPG) cell includes an input control circuit having an input coupled to an input signal and an output. The input control circuit includes has transistors configured as a first inverter transmission gate. The transistors also connect in series at least one transistor controlled by a power gating signal. A first latch has an input coupled to the output of the input control circuit and an output. A transmission gate has an input coupled to the output of the first latch and an output that is an output of the SRPG cell. A second latch has an input coupled to the output of the transmission gate and an output that also is an output of the SRPG cell. A second inverter transmission gate has an input coupled to the output of the second latch.
1. A clock state independent (CSI) state retention power gated (SRPG) cell, comprising:
an input control circuit that receives an input signal, wherein the input control circuit comprises a plurality of transistors configured as a first inverter transmission gate, and at least one transistor serially connected to the plurality of transistors that is controlled by at least one power gating signal, wherein the input control circuit comprises first and second P-channel transistors, and first, second and third N-channel transistors, wherein the second P-channel transistor, the first P-channel transistor, the first N-channel transistor, the second N-channel transistor and the third N-channel transistor are sequentially series connected;
a first latch having an input coupled to an output of the input control circuit;
a transmission gate having an input coupled to an output of the first latch, wherein an output of the transmission gate comprises at least one output of the SRPG cell;
a second latch having an input coupled to the output of the transmission gate, wherein an output of the second latch comprises at least one output of the SRPG cell; and
a second inverter transmission gate having an input coupled to the output of the second latch and an output coupled to the first latch.
2. The CSI SRPG cell of claim 1 , wherein the first inverter transmission gate is controlled by at least one control signal obtained by a logical operation of a clock signal and the at least one power gating signal.
3. The CSI SRPG cell of claim 1 , wherein the input control circuit further comprises:
a third P-channel transistors series connected to the second P-channel transistor.
4. The CSI SRPG cell of claim 3 , wherein,
the gate of the first P-channel transistor is coupled to receive a first control signal, and the gate of the first N-channel transistor is coupled to receive a second control signal that is a complement of the first control signal;
the gate of the third P-channel transistor is coupled to receive a first power gating signal, and the gate of the third N-channel transistor is coupled to receive a second power gating signal that is a complement of the first power gating signal; and
the gates of the second P-channel and N-channel transistors are coupled to receive the input signal.
5. The CSI SRPG cell of claim 4 , wherein the first control signal is obtained by a logic AND operation of the clock signal and the second power gating signal.
6. The CSI SRPG cell of claim 1 , wherein,
the gate of the first P-channel transistor is coupled to receive a first control signal, and the gate of the first N-channel transistor is coupled to receive a second control signal that is a complement of the first control signal;
the gate of the third N-channel transistor is coupled to receive a second power gating signal; and
the gates of the second P-channel transistor and the second N-channel transistor are coupled to receive the input signal.
7. A non-clock state independent (CSI) state retention power gated (SRPG) cell, comprising:
an input control circuit that receives an input signal, wherein the input control circuit is a first transmission gate controlled by a clock signal, wherein the input control circuit comprises first and second P-channel transistors, and first, second and third N-channel transistors, wherein the second P-channel transistor, the first P-channel transistor, the first N-channel transistor, the second N-channel transistor and the third N-channel transistor are sequentially series connected;
a first latch having an input coupled to an output of the input control circuit;
a second transmission gate having an input coupled to an output of the first latch, wherein an output of the second transmission gate comprises at least one output of the SRPG cell;
a second latch having an input coupled to the output of the second transmission gate, wherein an output of the second latch comprises at least one output of the SRPG cell; and
an inverter transmission gate ( 20 ) having an input coupled to the output of the second latch and an output coupled to an input of the first latch.
8. The SRPG cell of claim 7 , wherein for a positive edge clock triggered SRPG cell, the clock signal is held high during assertion/de-assertion of a power gating signal, and the input control circuit is disabled.
9. The SRPG cell of claim 7 , wherein for a negative edge clock triggered SRPG cell, the clock signal is held low during assertion/de-assertion of a power gating signal, and the input control circuit is disabled.
10. A method of controlling a state retention power gated (SRPG) cell, comprising:
controlling an input control circuit using only a clock signal, wherein the input control circuit receives an input signal and wherein the input control circuit is a first transmission gate, wherein the input control circuit comprises first and second P-channel transistors, and first, second and third N-channel transistors, wherein the second P-channel transistor, the first P-channel transistor, the first N-channel transistor, the second N-channel transistor and the third N-channel transistor are sequentially series connected;
controlling a first latch using a control signal, wherein the first latch has an input coupled to an output of the input control circuit;
controlling a second transmission gate using the control signal, wherein the second transmission gate has an input coupled to an output of the first latch and an output that comprises at least one output of the SRPG cell;
controlling a second latch using the control signal, wherein the second latch has an input coupled to the output of the second transmission gate and an output that comprises at least one output of the SRPG cell; and
controlling an inverter transmission gate using a power gating signal, wherein the inverter transmission gate has an input coupled to the output of the second latch, and an output coupled to the input of the first latch.
11. The control method of claim 10 , wherein for a positive edge-clock-triggered non-CSI SRPG cell, the clock signal is held high during assertion/de-assertion of the power gating signal, and the input control circuit is disabled.
12. The control method of claim 10 , wherein for a negative edge, clock-triggered non-CSI SRPG cell, the clock signal is held low during assertion/de-assertion of the power gating signal, and the input control circuit is disabled.
13. The control method of claim 10 , wherein the control signal is obtained by a logic AND operation of the clock signal and the power gating signal.