System for functional reset across multiple clock domains
View Patent ↗A system for synchronizing a functional reset between first and second clock domains that operate on first and second clock signals, respectively. The system includes first, second and third synchronizer flip-flops that operate on the second clock signal. The first synchronizer flip-flop receives a functional reset signal generated by the first clock domain at its reset terminal and generates a low output signal. The low output signal causes the second synchronizer flip-flop and subsequently the third synchronizer flip-flop to generate low output signals at positive edges of the second clock signal. The low output signal generated by the third synchronizer flip-flop is used to reset the second clock domain.
1. A system for synchronizing a functional reset generated by a first chain of flip-flops that operate on a first clock signal, with a second chain of flip-flops that operate on a second clock signal, comprising:
a first flip-flop having an input terminal for receiving a logic high signal, a clock terminal for receiving the second clock signal and a reset terminal for receiving a functional reset signal from the first chain of flip-flops, wherein the first flip-flop is reset when the functional reset signal is asserted;
a second flip-flop having an input terminal connected to an output terminal of the first flip-flop and a clock terminal for receiving the second clock signal, wherein the second flip-flop generates a first logic low signal at an output terminal thereof, at a positive edge of the second clock signal; and
a third flip-flop having an input terminal connected to the output terminal of the second flip-flop for receiving the logic low signal and a clock terminal for receiving the second clock signal, wherein the third flip-flop generates a second logic low signal at an output terminal thereof, at a positive edge of the second clock signal,
wherein the output terminal of the third flip-flop is connected to reset terminals of the second chain of flip-flops for providing the second logic low signal thereto.
2. The system of claim 1 , further comprising a first logic circuit, connected to the output terminal of the third flip-flop, for inverting the second logic low signal and generating a logic high signal.
3. The system of claim 2 , further comprising a second logic circuit, connected to the first logic circuit, for inverting the logic high signal and generating a third logic low signal.
4. The system of claim 3 , further comprising a third logic circuit having a first input terminal connected to the second logic circuit for receiving the third logic low signal, a second terminal for receiving a power-on-reset (POR) signal and an output terminal connected to the reset terminals of the second chain of flip-flops.
5. The system of claim 4 , wherein the first and second logic circuits each comprise a NOT gate.
6. The system of claim 4 , wherein the third logic circuit comprises an AND gate.
7. The system of claim 1 , wherein the first and second clock signals are asynchronous.
8. An integrated circuit, comprising:
first and second chains of flip-flops that operate on first and second clocks signals, respectively; and
a synchronizer circuit, for synchronizing a functional reset generated by the first chain of flip-flops with the second chain of flip-flops, wherein the synchronizer circuit comprises:
a first flip-flop having an input terminal for receiving a logic high signal, a clock terminal for receiving the second clock signal and a reset terminal for receiving a functional reset signal from the first chain of flip-flops, wherein the first flip-flop is reset when the functional reset signal is asserted;
a second flip-flop having an input terminal connected to an output terminal of the first flip-flop and a clock terminal for receiving the second clock signal, wherein the second flip-flop generates a first logic low signal at an output terminal thereof, at a positive edge of the second clock signal; and
a third flip-flop having an input terminal connected to the output terminal of the second flip-flop for receiving the logic low signal and a clock terminal for receiving the second clock signal, wherein the third flip-flop generates a second logic low signal at an output terminal thereof, at a positive edge of the second clock signal,
wherein the output terminal of the third flip-flop is connected to reset terminals of the second chain of flip-flops for providing the second logic low signal thereto.
9. The integrated circuit of claim 8 , further comprising a first logic circuit, connected to the output terminal of the third flip-flop, for inverting the second logic low signal and generating a logic high signal.
10. The integrated circuit of claim 9 , further comprising a second logic circuit, connected to the first logic circuit, for inverting the logic high signal and generating a third logic low signal.
11. The integrated circuit of claim 10 , further comprising a third logic circuit having a first input terminal connected to the second logic circuit for receiving the third logic low signal, a second terminal for receiving a power-on-reset (POR) signal and an output terminal connected to the reset terminals of the second chain of flip-flops.
12. The integrated circuit of claim 11 , wherein the first and second logic circuits each comprise a NOT gate.
13. The integrated circuit of claim 11 , wherein the third logic circuit comprises an AND gate.
14. The integrated circuit of claim 8 , wherein the first and second clock signals are asynchronous.
15. An integrated circuit, comprising:
first and second chains of flip-flops that operate on first and second clocks signals, respectively; and
a synchronizer circuit, for synchronizing a functional reset generated by the first chain of flip-flops with the second chain of flip-flops, wherein the synchronizer circuit comprises:
a first flip-flop having an input terminal for receiving a logic high signal, a clock terminal for receiving the second clock signal and a reset terminal for receiving a functional reset signal from the first chain of flip-flops, wherein the first flip-flop is reset when the functional reset signal is asserted;
a second flip-flop having an input terminal connected to an output terminal of the first flip-flop and a clock terminal for receiving the second clock signal, wherein the second flip-flop generates a first logic low signal at an output terminal thereof, at a positive edge of the second clock signal; and
a third flip-flop having an input terminal connected to the output terminal of the second flip-flop for receiving the logic low signal and a clock terminal for receiving the second clock signal, wherein the third flip-flop generates a second logic low signal at an output terminal thereof, at a positive edge of the second clock signal, wherein the output terminal of the third flip-flop is connected to reset terminals of the second chain of flip-flops for providing the second logic low signal thereto;
a first logic circuit, connected to the output terminal of the third flip-flop, for inverting the second logic low signal and generating a logic high signal;
a second logic circuit, connected to the first logic circuit, for inverting the logic high signal and generating a third logic low signal; and
a third logic circuit having a first input terminal connected to the second logic circuit for receiving the third logic low signal, a second terminal for receiving a power-on-reset (POR) signal and an output terminal connected to the reset terminals of the second chain of flip-flops.
16. The integrated circuit of claim 15 , wherein the first and second logic circuits each comprise a NOT gate.
17. The integrated circuit of claim 15 , wherein the third logic circuit comprises an AND gate.
18. The integrated circuit of claim 15 , wherein the first and second clock signals are asynchronous.