IP Library Granted Patent US 9,106,089
Granted Patent B2
US 9,106,089 · App. 13/958,600 · Granted Aug 11, 2015

Self-adapting voltage amplifier and battery charger detection

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Quick Facts
Patent No.
US 9,106,089
App. No.
13/958,600
Granted
Aug 11, 2015
Kind
B2
Abstract

An amplifier applies a self-adapting voltage to an output terminal. A bias circuit provides a greater bias current in a first external connection condition, in the absence of a pull-up resistance connected to the output terminal, than when such a pull-up resistance is present. The amplifier applies a different voltage to the output terminal in the absence of a pull-up resistance than when such a pull-up resistance is present. The circuit can be used in a portable device for receiving charging current from a battery charger through a connector having a D+ pin for connection to the battery charger and connected to the amplifier output terminal for battery charger detection. The portable device can meet the USB battery charger specification rev. 1.2.

Claims (30)

1. A portable device for receiving charging current from a battery charger, the portable device comprising:

a connector having a D+ pin for connection to said battery charger; and

an amplifier for applying a voltage to said D+ pin during charger detection, and having a bias circuit for providing bias to said amplifier,

wherein said amplifier has a transconductance that is a function of said bias, and

wherein said bias circuit provides a first level of bias in the absence of a pull-up resistor in said battery charger connected to said D+ pin causing said amplifier to function at a first transconductance and apply a first voltage to said D+ pin, and said bias circuit provides a second level of bias in the presence of said pull-up resistor causing said amplifier to function at a second reduced transconductance and to enable said D+ pin to adopt a second voltage higher than said first voltage.

2. The portable device of claim 1 , wherein said amplifier has a non-inverting input connected to a source of a reference voltage, an inverting input, and a negative feedback loop connecting said D+ pin with said inverting input.

3. The portable device of claim 1 , wherein said bias circuit includes first and second bias modules for supplying respectively first and second bias currents in parallel to said amplifier, said first bias current being greater in the absence of said pull-up resistor than in the presence of said pull-up resistor.

4. The portable device of claim 3 , wherein said first module includes a first current source for supplying a reference bias current through a first current mirror and a shunt having a control electrode connected with said D+ pin for shunting at least a part of said first bias current away from said current mirror in the presence of said pull-up resistor.

5. The portable device of claim 1 , wherein said first voltage is between 0.5V and 0.7V when sourcing a current of at least 250 μA and said second voltage is between 2.0V and 3.6V when said D+ pin is connected to a voltage between 3.0V and 3.6V through a pull up resistance between 0.9 kΩ and 1.575 kΩ in the battery charger.

6. A portable device for receiving charging current from a universal serial bus (USB) battery charger, said device comprising:

a universal serial bus (USB) receptacle having a D+ pin for connection to said battery charger; and

an amplifier for applying a voltage to said D+ pin during charger detection, and having a bias circuit for providing bias to said amplifier,

wherein said amplifier has a transconductance that is a function of said bias, and

wherein said bias circuit provides a first level of bias in the absence of a pull-up resistor in said battery charger connected to said D+ pin causing said amplifier to function at a first transconductance and apply a first voltage to said D+ pin, and said bias circuit provides a second level of bias in the presence of said pull-up resistor causing said amplifier to function at a second reduced transconductance and to enable said D+ pin to adopt a second voltage higher than said first voltage.

7. The portable device of claim 6 , wherein said amplifier has an input connected to a source of a reference voltage and a negative feedback loop connecting said D+ pin with an inverting input of said amplifier.

8. The portable device of claim 6 , wherein said bias circuit includes first and second bias modules for supplying respectively first and second bias currents in parallel to said amplifier, said first bias current being greater in the absence of said pull-up resistor than in the presence of said pull-up resistor.

9. The portable device of claim 8 , wherein said first module includes a first current source for supplying a reference bias current through a first current mirror and a shunt having a control electrode connected with said D+ pin for shunting at least a part of said first bias current away from said current mirror in the presence of said pull-up resistor.

10. The portable device of claim 6 , wherein said portable device is compliant with the USB battery charging specification revision 1.2.

11. The portable device of claim 6 , wherein said first voltage is between 0.5V and 0.7V when sourcing a current of at least 250 μA and said second voltage is between 2.0V and 3.6V when said D+ pin is connected to a voltage between 3.0V and 3.6V through a pull up resistance between 0.9 kΩ and 1.575 kΩ in the battery charger.

12. An amplifier for applying an output voltage to an output terminal, the amplifier comprising:

first and second bias modules for providing first and second bias currents in parallel to the amplifier; and

a shunt having a control electrode connected with the output terminal for shunting at least a part of the first bias current away from the first bias module in a first external connection condition at the output terminal,

wherein the amplifier applies to the output terminal a different level of said output voltage in the first external connection condition than in a second external connection condition at the output terminal.

13. The amplifier of claim 12 , further comprising a non-inverting input connected to a source of a reference voltage, an inverting input, and a negative feedback loop that connects the output terminal with the inverting input.

14. The amplifier of claim 13 , wherein the amplifier includes first and subsequent amplifier stages, and the shunt provides a positive feedback loop from the output terminal to the first amplifier stage through the first bias module, and wherein the positive feedback loop weakens the negative feedback of the negative feedback loop when the external pull-up resistor is connected between the output terminal and the external voltage source.

15. The amplifier of claim 12 , wherein the first and second bias modules comprise first and second current mirrors and first and second reference current sources respectively, each of the current mirrors having a reference current branch receiving reference current from the respective reference current source and a current mirror branch, and the shunt being connected to shunt current from the first reference current source away from the reference current branch of the first current mirror.

16. The amplifier of claim 15 , wherein the shunt includes a field-effect transistor (FET) having the control electrode, and a source-drain current flow path connected in parallel with the reference current branch of the first current mirror.

17. The amplifier of claim 16 , wherein the amplifier includes first and subsequent amplifier stages, and the shunt provides a positive feedback loop from the output terminal to the first amplifier stage amplifier through the first bias module.

18. The amplifier of claim 12 , wherein the first external connection condition corresponds to the presence of an external pull-up resistor connected between the output terminal and an external voltage source, and the second external connection condition corresponds to the absence of the pull-up resistor and a load connected to the output terminal.

19. The amplifier of claim 12 , wherein the level of the output voltage is greater in the first external connection condition when the shunt shunts the part of the first bias current away from the first bias module than in the second external connection condition.

Assignments (17)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
MERGER Recorded Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PCT NUMBERS IB2013000664, US2013051970, US201305935 PREVIOUSLY RECORDED AT REEL: 037444 FRAME: 0787. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Oct 17, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 040450/0715 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
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SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 13, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 13, 2013
From: FREESCALE SEMICONDUCTOR, INC.
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SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 4, 2013
From: ZHANG, WENZHONG; ZHANG, SHAYAN; ZHAO, YI
To: FREESCALE SEMICONDUCTOR, INC.
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