Granted Patent B1

US 8,877,585 · App. 13/969,180 · Granted Nov 4, 2014

Abstract

Claims (70)

1. A method of making a semiconductor structure using a substrate having a non-volatile memory (NVM) portion, a high voltage portion, a medium voltage portion, and a logic portion, comprising:

growing a first oxide on a major surface of the substrate in the NVM portion, the high voltage portion, the medium voltage portion, and logic portion;

depositing a first conductive layer over the first oxide in the NVM portion, the high voltage portion, the medium voltage portion, and the logic portion;

patterning and etching the first conductive layer to expose the high voltage portion and the medium voltage portion;

growing a second oxide in the NVM portion, the high voltage portion, the medium voltage portion, and the logic portion;

masking the high voltage portion;

etching the second oxide from the NVM portion, medium voltage portion, and the logic portion while the high voltage portion is masked;

growing a third oxide in the NVM portion, the high voltage portion, the medium voltage portion, and the logic portion;

masking the high voltage portion and the medium voltage portion;

etching the third oxide and the first conductive layer in the NVM portion and the logic portion while the high voltage portion and the medium voltage portion remain masked;

growing a fourth oxide in the NVM portion, the high voltage portion, the medium voltage portion, and the logic portion;

fabricating a memory cell requiring high voltage during operation in the NVM portion, the fabricating including using a protective layer over the high voltage portion, the medium voltage portion, and the logic portion when performing an implant in a second conductive layer in the NVM portion;

removing the protective layer over the high voltage portion, the medium voltage portion, and the logic portion;

patterning transistor gates in the high voltage portion and the medium voltage portion;

depositing a protective mask in the NVM portion, the high voltage portion, and the medium voltage portion; and

forming a logic device in the logic portion while the protective mask remains in the NVM portion, the high voltage portion, and the medium voltage portion.

2. The method of claim 1 , wherein the fabricating the memory cell further comprises:

forming a select gate by implanting the second conductive layer and patterning the second conductive layer and the fourth oxide;

forming a charge storage layer over the select gate and the substrate in the NVM portion, and in the high voltage portion, the medium voltage portion, and the logic portion;

depositing a third conductive layer over the charge storage layer in the NVM portion, the high voltage portion, the medium voltage portion, and the logic portion;

patterning the third conductive layer and the charge storage layer to form a control gate over a remaining portion of the charge storage layer and a portion of the select gate in the NVM portion, and to remove the charge storage layer and the third conductive layer in the high voltage portion, the medium voltage portion, and the logic portion.

3. The method of claim 2 , wherein the charge storage layer includes one of a group consisting of discrete storage elements between top and bottom layers of dielectric and a continuous storage element between top and bottom layers of dielectric.

4. The method of claim 2 , wherein the fabricating the memory cell further comprises:

depositing a layer of polysilicon for the third conductive layer.

5. The method of claim 1 , wherein the protective layer includes photoresist.

6. The method of claim 1 , wherein the protective mask includes a nitride layer and an oxide layer.

7. The method of claim 1 , wherein the forming the logic device comprises:

forming a high k dielectric over the logic portion;

forming a barrier layer over the high k dielectric; and

patterning the barrier layer.

8. The method of claim 7 , wherein the forming the logic device further comprises:

forming a polysilicon layer over the barrier layer; and

patterning the polysilicon layer and the high k dielectric, wherein the patterning the polysilicon layer and the high k dielectric is aligned with the patterning the barrier layer to leave a gate stack.

9. The method of claim 1 , wherein the fabricating the memory cell further comprises:

depositing a layer of polysilicon for the second conductive layer.

10. The method of claim 1 , wherein the second oxide is grown on the first conductive layer in the NVM portion and the logic portion.

11. A method of making a semiconductor structure using a substrate having a non-volatile memory (NVM) portion, a first high voltage portion, a second high voltage portion and a logic portion, comprising:

forming a first conductive layer over an oxide layer on a major surface of the substrate in the NVM portion, the first and second high voltage portions, and logic portion;

fabricating a memory cell in the NVM portion while the first conductive layer remains in the first and second high voltage portions and the logic portion;

patterning the first conductive layer to form transistor gates in the first and second high voltage portions;

forming a protective mask over the NVM portion and the first and second high voltage portions; and

forming a transistor gate in the logic portion while the protective mask remains in the NVM portion and the first and second high voltage portions.

12. The method of claim 11 , wherein the fabricating the memory cell further comprises:

forming a select gate by implanting a portion of the first conductive layer and patterning the first conductive layer;

forming a charge storage layer over the select gate and the substrate in the NVM portion, and in the first and second voltage portions, and the logic portion;

depositing a second conductive layer over the charge storage layer in the NVM portion, the first and second high voltage portions, and the logic portion;

patterning the second conductive layer and the charge storage layer to form a control gate over a remaining portion of the charge storage layer and a portion of the select gate in the NVM portion, and to remove the charge storage layer and the second conductive layer in the first and second high voltage portions and the logic portion.

13. The method of claim 12 , wherein the charge storage layer includes one of a group consisting of discrete storage elements between top and bottom layers of dielectric and a continuous storage element between top and bottom layers of dielectric.

14. The method of claim 12 , wherein the patterning the first conductive layer for the fabricating the memory cell and the patterning the first conductive layer to form the transistor gates in the first and second high voltage portions is performed concurrently.

15. The method of claim 11 , wherein the fabricating the memory cell includes patterning the first conductive layer to form a gate for the memory cell, and the patterning the first conductive layer to form the transistor gates in the first and second high voltage portions is performed concurrently with the patterning the first conductive layer to form the gate for the memory cell.

16. The method of claim 11 , wherein the protective mask includes a nitride layer and an oxide layer.

17. The method of claim 11 , wherein the forming the transistor gate comprises:

forming a high k dielectric;

forming a barrier layer over the high k dielectric;

forming a polysilicon layer over the barrier layer; and

patterning the high k dielectric, the barrier layer, and the polysilicon layer.

18. The method of claim 11 , wherein:

the first conductive layer is a layer of polysilicon.

19. The method of claim 11 , wherein:

the fabricating includes using a protective layer over the first and second high voltage portions and the logic portion when performing an implant in a second conductive layer in the NVM portion.

20. The method of claim 11 , further comprising:

before fabricating the memory cell:

patterning and etching the first conductive layer to expose the first and second high voltage portions;

growing a second oxide in the NVM portion, the first and second high voltage portions, and the logic portion;

masking a first of the high voltage portions;

etching the second oxide from the NVM portion, a second of the high voltage portions, and the logic portion while the first of the high voltage portions is masked;

growing a third oxide in the NVM portion, the first and second high voltage portions, and the logic portion;

masking the first and second high voltage portions;

etching the third oxide and the first conductive layer in the NVM portion and the logic portion while the first and second high voltage portions remain masked; and

growing a fourth oxide in the NVM portion, the first and second high voltage portions, and the logic portion.

Assignments (17)