Device and method for computing a function value of a function
View Patent ↗A device is provided for computing a function value of a function F. The device includes a memory, a truncator unit, a selector unit, and an evaluator unit. The memory contains a look-up table comprising a set of entries, each entry having associated with it a domain and an approximation function for approximating F on the associated domain. The truncator unit is arranged to truncate or round a first value X1 to generate a second value X2. The selector unit is arranged to select an entry of the lookup-table according to the second value X2, thus selecting the approximation function that is associated with the selected entry. The evaluator unit is arranged to determine the function value of the selected approximation function at the first value X1.
1. A device for computing a function value of a function F, comprising:
a memory storing a look-up table comprising a first set of entries storing numbers in a first fixed-point format and a second set of entries storing numbers in a second fixed-point format, each entry of the first and second set of entries of which entries having associated with a corresponding domain and a corresponding approximation function for approximating the function F on the associated domain;
a truncator unit arranged to truncate or round a first value X1 to generate a second value X2;
a selector unit, coupled to the truncator unit and the memory, and arranged to select an entry of the look-up table according to the second value X2, thus selecting the approximation function that is associated with the selected entry;
a first fixed-point to floating-point converter comprising a first register, a second register, and a first multiplexer, the first register and the second register coupled to the first multiplexer and the first multiplexer configured to select contents of the first or second register, wherein the first register stores a first representation of a first set number of the first set of entries, the second register stores a second representation of the first set number of the first set of entries, and the first multiplexer is configured to select one of the first or second registers to output a floating-point representation of the first set number based on one or more of an index of the first set of entries or a characteristic of the first set number;
a second fixed-point to floating-point converter comprising a third register, a fourth register, and a second multiplexer, the third register and the fourth register coupled to the second multiplexer and the second multiplexer configured to select contents of the third or fourth register, wherein the third register stores a first representation of a second set number of the second set of entries, the fourth register stores a second representation of the second set number of the second set of entries, and the second multiplexer is configured to select one of the third or fourth registers to output a floating-point representation of the second set number based on one or more of an index of the second set of entries or a characteristic of the second set number; and
an evaluator unit, coupled to the selector unit, and arranged to determine the function value of the selected approximation function at the first value X1.
2. The device as set forth in claim 1 , wherein the truncator unit is arranged to extract a subset of bits from the first value X1.
3. The device as set forth in claim 1 , wherein the domains associated with subsequent entries are adjoining intervals.
4. The device as set forth in claim 1 , wherein at least one of the approximation functions minimizes
a maximum absolute error on the associated domain, or
an average quadratic error on the associated domain.
5. The device as set forth in claim 1 , wherein at least one of the approximation functions is a linear function.
6. The device as set forth in claim 5 , wherein the evaluator unit comprises a multiply-accumulate unit for evaluating said linear function.
7. The device as set forth in claim 1 , comprising a preconditioner unit which comprises
a first preconditioner arranged to determine the first value X1 from a third value X3 such that the first value X1 is within a predefined range, and
a second preconditioner arranged to determine an approximate or exact function value of the function F at the third value X3 from the determined function value of the selected approximation function at the first value X1.
8. The device as set forth in claim 1 , wherein the function F is the logarithm to a base Q.
9. The device as set forth in claim 8 , wherein Q equals two.
10. The device as set forth in claim 8 , comprising a preconditioner unit which comprises
a first preconditioner arranged to determine the first value X1 and an exponent P1 from a third value X3 such that X3=X1*Q**P1, and
a second preconditioner arranged to add the exponent P1 to the determined function value of the selected approximation function at the first value X1.
11. The device as set forth in claim 1 , integrated in a digital signal processor.