Redistributed chip packages containing multiple components and methods for the fabrication thereof
View Patent ↗Embodiments of a method for fabricating Redistributed Chip Packages are provided, as are embodiments of Redistributed Chip Packages. In one embodiment, the method includes the steps/processes of embedding a first semiconductor die and a microelectronic component in a molded panel having a frontside, the first semiconductor die comprising a plurality of bond pads over which a plurality of raised contacts has been formed. The frontside of the molded panel is polished to impart the molded panel with a substantially planar surface through which the terminals of the microelectronic component and the plurality of raised contacts are exposed. Finally, at least one redistribution layer is build or produced over the substantially planar surface to electrically interconnect the first semiconductor die and the microelectronic component.
1. A method for fabricating a Redistributed Chip Package, the method comprising:
embedding a first semiconductor die and a microelectronic component in a molded panel having a frontside, the first semiconductor die comprising a plurality of bond pads over which a plurality of raised contacts has been formed;
polishing the frontside of the molded panel to impart the molded panel with a substantially planar surface through which the terminals of the microelectronic component and the plurality of raised contacts are exposed; and
building at least one redistribution layer over the substantially planar surface, the at least one redistribution layer electrically interconnecting the first semiconductor die and the microelectronic component.
2. The method of claim 1 wherein the plurality of raised contacts comprise a plurality of coined stud bumps.
3. The method of claim 1 wherein the plurality of raised contacts comprise a plurality of plated pillars.
4. The method of claim 1 wherein a dielectric filler material has been deposited over the first semiconductor die and fills, at least in substantial part, the space between the plurality of raised contacts.
5. The method of claim 1 wherein polishing the frontside of the molded panel comprises removing a predetermined thickness between about 3 and about 10 microns from the frontside of the molded panel.
6. The method of claim 1 wherein polishing the frontside of the molded panel comprises utilizing a chemical mechanical planarization (“CMP”) process to remove a predetermined thickness from the frontside of the molded panel, while also removing an upper portion of the raised contacts and an upper portion of the terminals of the microelectronic component.
7. The method of claim 1 wherein the diameter of each raised contact is substantially equivalent to the width of the bond pad over which the raised contact has been formed.
8. The method of claim 1 wherein the raised contacts are formed to have a height between about 1 and about 10 microns.
9. The method of claim 1 wherein the microelectronic component comprises a passive microelectronic device, and wherein the at least one redistribution layer electrically interconnects the semiconductor die and the passive device to produce a System-In-Package.
10. The method of claim 1 wherein the microelectronic component comprises a leaded package.
11. The method of claim 10 wherein the leaded package is selected from the group consisting of a J-lead package and a gullwing package.
12. The method of claim 1 further comprising:
forming the plurality of raised contacts over the first semiconductor die while the first semiconductor die remains joined to a plurality of other semiconductor die in the form of a non-singulated wafer; and
singulating the non-singulated wafer to produce a plurality semiconductor die over which a plurality of raised contacts has been formed, the plurality of semiconductor die including the first semiconductor die.
13. A method for fabricating a Redistributed Chip Package (RCP), the method comprising:
forming a plurality of raised contacts over the surface of a wafer containing a plurality of semiconductor die;
singulating the wafer to yield a plurality of singulated semiconductor die each having a plurality of raised contacts formed thereover;
encapsulating the plurality of singulated semiconductor die and a plurality of additional microelectronic devices in a molded panel, the plurality of additional microelectronic devices each including a number of microelectronic device terminals;
polishing the frontside of the molded panel to create a substantially planar surface through which the plurality of raised contacts and the microelectronic device terminals are exposed;
producing one or more redistribution layers over the molded panel including interconnect lines electrically coupled to the plurality of raised contacts and the microelectronic device terminals;
forming contact arrays over the plurality of redistribution layers in ohmic contact with the interconnect lines; and
separating the panel into a plurality of RCP packages each containing at least one semiconductor device and at least one additional microelectronic device embedded within a molded body.
14. The method of 13 further comprising depositing a dielectric filler material over the frontside surface of the semiconductor die surrounding the plurality of raised contacts prior to encapsulating the plurality of singulated semiconductor die and the plurality of additional microelectronic devices in the molded panel.
15. A Redistributed Chip Package, comprising:
a microelectronic component having a plurality of terminals;
a semiconductor die having a plurality of bond pads and disposed adjacent the microelectronic component;
a plurality of raised contacts located over the semiconductor die in ohmic contact with the plurality of bond pads;
a molded body in which the microelectronic component and the semiconductor die are embedded, the molded body having a substantially planar frontside surface through which the plurality of terminals of the microelectronic component and the plurality of raised contacts are exposed; and
at least one redistribution layer located over the substantially planar frontside surface and electrically interconnecting the microelectronic component and the semiconductor die.
16. The multi-component microelectronic package of claim 15 wherein the plurality of raised contacts comprises a plurality of coined stud bumps.
17. The multi-component microelectronic package of claim 15 wherein the plurality of raised contacts comprises a plurality of plated pillars.
18. The multi-component microelectronic package of claim 17 wherein each of the plurality of plated pillars has a height between about 1 and about 15 microns.
19. The multi-component microelectronic package of claim 15 further comprising a dielectric filler disposed over the microelectronic die and between the plurality of raised contacts.
20. The multi-component microelectronic package of claim 15 wherein the terminals of the microelectronic component are imparted with flat polished regions that are exposed through and substantially co-planar with the substantially planar frontside surface of the molded body.