IP Library Granted Patent US 9,108,842
Granted Patent B2
US 9,108,842 · App. 13/946,729 · Granted Aug 18, 2015

Reducing microelectromechanical systems stiction by formation of a silicon carbide layer

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Quick Facts
Patent No.
US 9,108,842
App. No.
13/946,729
Granted
Aug 18, 2015
Kind
B2
Abstract

A mechanism is provided for reducing stiction in a MEMS device by forming a near-uniform silicon carbide layer on silicon surfaces using carbon from TEOS-based silicon oxide sacrificial films used during fabrication. By using the TEOS as a source of carbon to form an antistiction coating, all silicon surfaces can be coated, including those that are difficult to coat using standard self-assembled monolayer (SAM) processes (e.g., locations beneath the proof mass). Controlled processing parameters, such as temperature, length of time for annealing, and the like, provide for a near-uniform silicon carbide coating not provided by previous processes.

Claims (36)

1. A method for manufacturing a microelectromechanical systems (MEMS) device, the method comprising:

forming a first silicon layer over a substrate;

forming a sacrificial layer over the first silicon layer, wherein the sacrificial layer comprises silicon oxide deposited using tetraethyl orthosilicate (TEOS) gas;

annealing the first silicon layer and the sacrificial layer wherein said annealing comprises heating the first silicon layer and the sacrificial layer to a temperature sufficient to form a silicon carbide layer at an interface region between the first silicon layer and the sacrificial layer, wherein the silicon carbide layer comprises carbon provided by the sacrificial layer.

2. The method of claim 1 wherein said annealing comprises heating the first silicon layer and the sacrificial layer to at least 1000 C for at least one hour.

3. The method of claim 2 where said annealing comprises heating the first silicon layer and the sacrificial layer to at least 1180 C for at least two hours.

4. The method of claim 1 wherein said annealing comprises heating the first silicon layer and the sacrificial layer to a temperature sufficient to form the silicon carbide layer to have a thickness of 300-500 Å.

5. The method of claim 1 further comprising forming a second silicon layer over the sacrificial layer.

6. The method of claim 5 further comprising:

annealing the second silicon layer and the sacrificial layer wherein said annealing comprises heating the second silicon layer and the sacrificial layer to a temperature sufficient to form a silicon carbide layer at an interface region between the second silicon layer and the sacrificial layer, wherein the silicon carbide layer comprises carbon provided by the sacrificial layer.

7. The method of claim 5 further comprising:

removing the sacrificial layer subsequent to said forming the second silicon layer, wherein said removing comprises using one of a wet etch or a vapor phase etch (VPE).

8. The method of claim 1 further comprising:

removing the sacrificial layer subsequent to said annealing the first silicon layer and the sacrificial layer, wherein said removing comprises using one of a wet etch or a VPE.

9. The method of claim 1 further comprising:

forming a first insulating layer over the substrate, wherein the first silicon layer is one of a polysilicon layer or an amorphous silicon layer formed over the first insulating layer; and

forming a second insulating layer over at least a portion of the first silicon layer.

10. A microelectromechanical systems (MEMS) device comprising:

a fixed surface comprising a first silicon layer formed over a substrate and a first insulating layer formed over at least a portion of the first silicon layer;

a moveable body comprising a second silicon layer providing a major surface facing the fixed surface; and

a uniform silicon carbide layer formed on at least one of the first silicon layer and the major surface of the second silicon layer, wherein the uniform silicon carbide layer comprises carbon from a TEOS sacrificial layer.

11. The MEMS device of claim 10 wherein the uniform silicon carbide layer is between about 300 Å to about 500 Å in thickness.

12. The MEMS device of claim 10 wherein the uniform silicon carbide layer is formed at least on the major surface of the second silicon layer.

13. The MEMS device of claim 10 wherein the MEMS device comprises one or more of an accelerometer and a gyroscope.

14. A method of manufacturing a microelectromechanical systems (MEMS) device, the method comprising:

forming a fixed surface comprising a first layer of silicon;

forming a movable body providing a major surface facing the fixed surface, wherein at least a portion of the major surface is configured to contact at least a portion of the fixed surface and the at least a portion of the major surface comprises a second layer of silicon;

forming a sacrificial layer between the fixed surface and the movable body, wherein the sacrificial layer comprises carbon and silicon oxide deposited using tetraethyl orthosilicate (TEOS) gas; and

forming at least one of the first layer of silicon or the second layer of silicon such that the carbon from the sacrificial layer forms a uniform layer of silicon carbide on at least one of the first layer or second layer of silicon.

15. The method of claim 14 wherein said forming at least one of the first layer of silicon or the second layer of silicon such that the carbon from the sacrificial layer forms a uniform layer of silicon carbide on at least one of the first layer or second layer of silicon further comprises:

annealing the first layer of silicon and the sacrificial layer, wherein said annealing comprises heating the first silicon layer and the sacrificial layer to a temperature sufficient for the silicon carbide layer to form at an interface between the first silicon layer and the sacrificial layer.

16. The method of claim 15 wherein said annealing comprises heating the first layer of silicon and the sacrificial layer to at least 1000 C for at least one hour.

17. The method of claim 16 where said annealing comprises heating the first layer of silicon and the sacrificial layer to at least 1180 C for at least two hours.

18. The method of claim 15 wherein said annealing comprises heating the first layer of silicon and the sacrificial layer to a sufficient temperature and a time sufficient to form a silicon carbide layer having a thickness of 300-500 Å.

19. The method of claim 14 wherein said forming at least one of the first layer of silicon or the second layer of silicon such that the carbon from the sacrificial layer forms a uniform layer of silicon carbide on at least one of the first layer or second layer of silicon further comprises:

annealing the second layer of silicon and the sacrificial layer, wherein said annealing comprises heating the second silicon layer and the sacrificial layer to a temperature sufficient for the silicon carbide layer to form at an interface between the second silicon layer and the sacrificial layer.

Assignments (18)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PCT NUMBERS IB2013000664, US2013051970, US201305935 PREVIOUSLY RECORDED AT REEL: 037444 FRAME: 0787. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Oct 17, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
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SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 13, 2013
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