Quad flat semiconductor device with additional contacts
View Patent ↗A Quad Flat Package (QFP) semiconductor device has a multi-stepped lead frame for forming rows of external contacts. A semiconductor die is attached to a die pad of the lead frame and electrically connected to lead with bond wires. The die and bond wires are encapsulated with a mold compound and then multiple cuts are made to the lead frame to form the rows of external contacts.
1. A surface mount semiconductor device, comprising:
a semiconductor die having an active face with die bond pads;
a package body having top and bottom surfaces, a side surface having quadrangular sides, and a step surface between the top and bottom surfaces and adjacent to the side surface at a level offset from the bottom surface, wherein the die is embedded within the package body;
a plurality of electrical leads that allow for connection to an external electrical circuit, wherein the electrical leads are connected with first ones of the die bond pads, and wherein the electrical leads have inner ends supported in the package body at the step surface and outer lead ends that project from at least two opposite side surfaces; and
at least a first set of exposed electrical contacts exposed in the bottom surface in at least two rows adjacent respectively to the at least two opposite side surfaces for connection to the external electrical circuit, wherein the first set of exposed contacts are connected with second ones of the die bond pads, and wherein the first set of exposed contacts have outer ends positioned in the package body at the step surface and aligned with but spaced from respective inner ends of the electrical leads at an adjacent side surface of the at least two opposite side surfaces by a saw street formed at the step surface.
2. The semiconductor device of claim 1 , wherein the electrical leads extend outside the package body from an intermediate level of the side surface, down to a level of the bottom surface.
3. The semiconductor device of claim 2 , wherein the intermediate level of the side surface is higher than the level of the step surface relative to the level of the bottom surface.
4. The semiconductor device of claim 1 , wherein the first set of exposed contacts have inner ends exposed in the bottom surface.
5. The semiconductor device of claim 1 , further comprising bond wires that connect the die bond pads with the electrical leads and the first set of exposed contacts respectively.
6. The semiconductor device of claim 5 , wherein the bond wires are attached to the electrical leads farther from a middle of the bottom surface than the inner ends of the electrical leads.
7. The semiconductor device of claim 6 , wherein the bond wires connect to the outer ends of the first set of exposed contacts.
8. The semiconductor device of claim 1 , further comprising at least one further set of exposed electrical contacts that is exposed in the bottom surface in at least two rows adjacent respectively to the opposite side surface for connection to the external electrical circuit, wherein the further set of exposed contacts are connected with third ones of the die bond pads, and the rows of the further set of exposed contacts are positioned in the bottom surface closer to a middle of the bottom surface than the rows of the first set of exposed contacts.
9. The semiconductor device of claim 8 , wherein additional bond wires connect the third die bond pads with the further exposed contacts set at positions closer to the middle of the bottom surface than the first set of exposed contacts.