IP Library Granted Patent US 9,722,648
Granted Patent B2
US 9,722,648 · App. 13/985,990 · Granted Aug 1, 2017

Integrated circuit device, electronic device and method for frequency detection

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Quick Facts
Patent No.
US 9,722,648
App. No.
13/985,990
Granted
Aug 1, 2017
Kind
B2
Abstract

An integrated circuit comprises a frequency detector. The frequency detector comprises a timer state machine unit operably couplable to a timer and arranged to receive an incoming carrier signal; determine whether the incoming carrier signal comprises a valid frequency; generate a valid carrier indication when the incoming carrier signal is determined as having a valid frequency; and adjust the timer between at least a first timing mode of operation and a second timing mode of operation of the frequency detector in response to the determination.

Claims (38)

1. An integrated circuit device comprising:

a frequency detector; wherein the frequency detector comprises:

a timer state machine unit coupled to a timer and arranged to receive an incoming carrier signal, determine whether the incoming carrier signal comprises a valid frequency, generate a valid carrier indication when the incoming carrier signal is determined as having said valid frequency, and continuously switch operation of the timer between at least a first timing mode of operation and a second timing mode of operation of the frequency detector in response to the determination,

wherein the detector determines whether the incoming carrier signal comprises said valid frequency in the first timing mode of operation based on a first number of carrier signal edges of the incoming carrier signal, and determines whether the incoming carrier signal comprises said valid frequency in the second timing mode of operation based on a second number of carrier signal edges of the incoming carrier signal, the second number different than the first.

2. The integrated circuit device of claim 1 wherein

the first timing mode of operation is an averaging mode of operation whereby the frequency detector determines whether the incoming carrier signal comprises said valid frequency by averaging the determination across a plurality of carrier signal edges of the incoming carrier signal.

3. The integrated circuit device of claim 2 wherein a number of the plurality of carrier signal edges to be averaged over in the first timing mode of operation is programmable.

4. The integrated circuit device of claim 1 wherein

in the second timing mode of operation the frequency detector determines whether the incoming carrier signal comprises said valid frequency by performing at least one determination on a single carrier signal edge.

5. The integrated circuit device of claim 1 wherein the frequency detector comprises a tunable timer.

6. The integrated circuit device of claim 5 , wherein a frequency of operation of the tunable timer is controllable in response to a determination of a signal quality of the incoming carrier signal.

7. The integrated circuit device of claim 1 wherein the frequency detector is a digital frequency detector.

8. The integrated circuit device of claim 1 wherein

the timer state machine unit is arranged to selectively switch between at least the first mode of operation and the second mode of operation of the frequency detector in determining whether the incoming carrier signal comprises said valid frequency.

9. The integrated circuit device of claim 1 further comprising comparison circuit arranged to compare a number of incoming carrier signal carrier edges counted over a validation period.

10. The integrated circuit device of claim 9 wherein the comparison circuit is operably coupled to a capacitive network and the timer state machine unit, such that the timer state machine unit switches between a first capacitor of the capacitive network and a second capacitor of the capacitive network to effect a timing mode change between the at least first timing mode of operation and the second timing mode of operation of the frequency detector.

11. The integrated circuit device of claim 10 wherein the timer state machine unit switches between a first capacitor of the capacitive network and a second capacitor of the capacitive network effect a change from a high-speed detection to a low-speed detection of the frequency detector.

12. The integrated circuit device of claim 1 wherein the timer state machine unit is further arranged to further re-start an incoming carrier signal detection operation of the frequency detector following a generation of an error signal or following a positive carrier validation having been confirmed.

13. The integrated circuit device of claim 1 wherein the timer state machine unit continuously and repetitively switches between alternate received carrier signal determination modes.

14. The integrated circuit device of claim 1 wherein the timer state machine unit continuously and repetitively switches between alternate received carrier signal determination modes in response to dynamic programming.

15. A method for frequency detection of a frequency detector, the method comprising:

receiving an incoming carrier signal;

determining whether the incoming carrier signal comprises a valid frequency;

generating a valid carrier indication when the incoming carrier signal is determined as having said valid frequency; and

continuously switching between at least a first timing mode of operation and a second timing mode of operation of a timer included at the frequency detector in response to the determination wherein

determining whether the incoming carrier signal comprises said valid frequency in the first timing mode of operation is based on a first number of carrier signal edges of the incoming carrier signal and determining whether the incoming carrier signal comprises said valid frequency in the second timing mode of operation is based on a second number of carrier signal edges of the incoming carrier signal the second number different than the first.

16. An electronic device including a frequency detector, the frequency detector comprising:

a timer state machine unit coupled to a timer and arranged to receive an incoming carrier signal, determine whether the incoming carrier signal comprises a valid frequency,

generate a valid carrier indication when the incoming carrier signal is determined as having said valid frequency, and continuously switch operation of the timer to select between at least a first timing mode of operation and a second timing mode of operation of the frequency detector in response to the determination;

wherein the first timing mode of operation is an averaging mode of operation whereby the frequency detector determines whether the incoming carrier signal comprises said valid frequency by averaging the determination across a plurality of carrier signal edges of the incoming carrier signal; and

wherein in the second timing mode of operation the frequency detector determines whether the incoming carrier signal comprises said valid frequency by performing at least one determination on a single carrier signal edge.

17. The method of claim 15 , wherein

the first timing mode of operation is an averaging mode of operation whereby the frequency detector determines whether the incoming carrier signal comprises said valid frequency by averaging the determination across a plurality of carrier signal edges of the incoming carrier signal.

18. The method of claim 15 , wherein

in the second timing mode of operation the frequency detector determines whether the incoming carrier signal comprises said valid frequency by performing at least one determination on a single carrier signal edge.

19. The method of claim 15 , wherein a number of the plurality of carrier signal edges to be averaged over in the first timing mode of operation is programmable.

20. The method of claim 15 , further comprising

selectively switching between at least the first mode of operation and the second mode of operation of the frequency detector in determining whether the incoming carrier signal comprises said valid frequency.

Assignments (27)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PCT NUMBERS IB2013000664, US2013051970, US201305935 PREVIOUSLY RECORDED AT REEL: 037444 FRAME: 0787. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Oct 17, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 040450/0715 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
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PATENT RELEASE Recorded Dec 21, 2015
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To: FREESCALE SEMICONDUCTOR, INC.
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From: FREESCALE SEMICONDUCTOR, INC.
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From: FREESCALE SEMICONDUCTOR, INC.
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From: FREITAS, PHILIPPE; DOARE, OLIVIER; ESCARPIT, VALERIE; LANDEZ, CHRISTOPHE; LHUILLIER, XAVIER
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