IP Library Granted Patent US 8,681,568
Granted Patent B2
US 8,681,568 · App. 14/041,697 · Granted Mar 25, 2014

Dynamic programming for flash memory

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Quick Facts
Patent No.
US 8,681,568
App. No.
14/041,697
Granted
Mar 25, 2014
Kind
B2
Abstract

A method is for operating a memory having a group of non-volatile memory cells. A first programming pulse is applied to a subset of the group of non-volatile memory cells. The subset needs additional programming. A portion of the subset still needing additional programming is identified. A ratio of the number of memory cells in the subset and the number of memory cells in the portion is determined. A size of a second programming pulse based on the ratio is selected. The second programming pulse is applied to the portion.

Claims (49)

1. A memory system, comprising:

a group of non-volatile memory cells

a memory controller configured to:

apply a first programming pulse to a subset of the group of non-volatile memory cells, wherein the subset needs additional programming;

identify a portion of the subset still needing additional programming;

determine a ratio of the number of memory cells in the subset and the number of memory cells in the portion;

select a size of a second programming pulse based on the ratio; and

apply the second programming pulse to the portion.

2. The system of claim 1 , wherein a difference between the portion and the subset is a number of non-volatile memory cells that became sufficiently programmed during the applying of the first programming pulse.

3. The system of claim 2 , wherein the non-volatile memory cells that became sufficiently programmed during the applying of the first programming pulse became sufficiently soft programmed.

4. The system of claim 2 , wherein the non-volatile memory cells that became sufficiently programmed during the applying of the first programming pulse became sufficiently programmed to be distinguishable from non-volatile memory cells that were in an erased condition.

5. The system of claim 2 , wherein the select the size comprises using the ratio to find the size of the second programming pulse in a look-up table.

6. The system of claim 5 , wherein the size of the second programming pulse is greater than that of the first programming pulse.

7. The system of claim 6 , wherein the size of the second programming pulse is greater by having a greater voltage.

8. The system of claim 6 , wherein the size of the second programming pulse is greater by having a greater duration.

9. The system of claim 1 , wherein the memory controller is further configured to:

identify a subportion of the portion still needing additional programming;

determine a ratio of the number of non-volatile memory cells in the subportion and the number of memory cells in the portion;

select a size of a third programming pulse based on the ratio of the number of memory cells in the portion and the number of non-volatile memory cells in the subportion; and

apply the third programming pulse to the subportion.

10. The system of claim 9 , wherein the size of the third programming pulse is greater than that of the second programming pulse.

11. The system of claim 9 , wherein the ratio of the number of memory cells in the subportion and the number of memory cells in the portion is the number of memory cells in the subportion divided by the number of non-volatile memory cells in the portion.

12. The system of claim 9 , wherein the ratio of the number of memory cells in the subportion and the number of memory cells in the portion is the number of non-volatile memory cells in the portion divided by the number of non-volatile memory cells in the subportion.

13. The system of claim 9 , further comprising determining if the applying the third programming pulse to the subportion resulted in all of the non-volatile memories in the subportion being sufficiently programmed.

14. The system of claim 9 , wherein the memory controller is further configured to:

identify a subset of the subportion still needing additional programming;

determine a ratio of the number of non-volatile memory cells in the subset and the number of memory cells in the subportion;

select a size of a fourth programming pulse based on the ratio of the number of memory cells in the subset and the number of memory cells in the subportion; and

apply the fourth programming pulse to the subset.

15. A memory system, comprising:

a plurality of non-volatile memory cells;

a memory controller operable to:

apply a first soft programming pulse to the plurality of non-volatile memory cells;

identify which non-volatile memory cells of the plurality of non-volatile memory cells that need additional soft programming;

find a ratio based on the number of non-volatile memory cells receiving the first soft programming pulse and the number of non-volatile memory cells still needing additional soft programming; and

apply additional soft programming pulses until all of the non-volatile memory cells of the plurality of memory cells have been soft programmed, wherein each additional soft programming pulse of the additional soft programming pulses has a size selected based on a ratio of the number of non-volatile memory cells to which an immediately previous additional software programming pulse was applied and the number of non-volatile memory cells still needing soft programming immediately after the immediately previous additional soft programming pulse was applied.

16. The system of claim 15 wherein a look-up table is used to determine the sizes of the additional soft programming pulses based on the ratio.

17. The system of claim 16 wherein the sizes vary in at least one of voltage magnitude and duration.

18. A memory system, comprising:

a memory array including a plurality of non-volatile memory cells that are functional for reading when in a programmed state or in an erased state;

an adjustable voltage supply coupled to the memory array;

a memory controller for:

directing the adjustable voltage supply to apply a first programming pulse to a subset of the plurality of non-volatile memory cells when the subset needs additional programming;

identifying a portion of the subset still needing additional programming;

determining a ratio of the number of memory cells in the subset and the number of memory cells in the portion;

selecting a voltage of a second programming pulse based on the ratio; and

directing the adjustable voltage supply to apply the second programming pulse to the portion.

19. The memory system of claim 18 , wherein the array comprises a plurality of pages, wherein the plurality of non-volatile memory cells is a first page of the plurality of pages.

20. The memory system of claim 19 , further comprising a look-up table that provides voltage magnitude information for programming pulses based on ratios provided by the memory controller to the look-up table.

Assignments (25)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
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CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
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MERGER Recorded Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PCT NUMBERS IB2013000664, US2013051970, US201305935 PREVIOUSLY RECORDED AT REEL: 037444 FRAME: 0787. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Oct 17, 2016
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