Wafer-level gate stress testing
View Patent ↗A method of testing a semiconductor device includes forming a test circuit over a semiconductor substrate. The test circuit includes a plurality of interconnects electrically connected to a set of device structures supported by the semiconductor substrate. A test, such as a gate stress or leakage current test, of each device structure is conducted with the test circuit. The plurality of interconnects are removed after conducting the test.
1. A method of testing a semiconductor device, the method comprising:
forming a test circuit over a semiconductor substrate, the test circuit comprising a plurality of interconnects electrically connected to a set of device structures supported by the semiconductor substrate;
conducting a test of each device structure with the test circuit; and
removing, through an etching or planarization procedure, the plurality of interconnects after conducting the test;
wherein:
the device structures comprise first and second gate structures;
the first and second gate structures comprise first and second gate oxide layers, respectively;
the first and second gate oxide layers have different thicknesses; and
conducting the test comprises:
applying a first stress voltage to the first gate structure via a first interconnect of the plurality of interconnects; and
applying a second gate stress voltage to the second gate structure via a second interconnect of the plurality of interconnects.
2. The method of claim 1 , wherein forming the test circuit comprises depositing a conductive material to form the plurality of interconnects, and wherein depositing the conductive material also forms contact plugs that establish a contact to each device structure.
3. The method of claim 2 , wherein removing the plurality of interconnects does not remove the contact plugs.
4. The method of claim 1 , wherein
conducting a test comprises conducting a gate stress test or a leakage current test of the first gate oxide layer and the second gate oxide layer with the test circuit.
5. The method of claim 1 , further comprising doping the semiconductor substrate to define a cross-under connector of the test circuit in the semiconductor substrate.
6. The method of claim 1 , further comprising forming a polysilicon cross-under connector of the test circuit supported by the semiconductor substrate.
7. The method of claim 1 , wherein one of the plurality of interconnects extends across a die boundary of the semiconductor substrate.
8. The method of claim 1 , wherein the test circuit comprises:
a first pad electrically connected to the set of device structures by the plurality of interconnects; and
a second pad electrically connected to the first pad by a return interconnect of the plurality of interconnects.
9. The method of claim 1 , further comprising forming a resistor of the test circuit in the semiconductor substrate, the resistor electrically connecting a respective interconnect of the plurality of interconnects to a corresponding device structure of the set of device structures.
10. The method of claim 1 , wherein conducting the test comprises:
applying a first voltage to the set of device structures; and
applying a second voltage to a bulk of the semiconductor substrate.
11. A method of fabricating a semiconductor device, the method comprising:
forming device regions in a semiconductor substrate;
forming device gate structures on the semiconductor substrate;
forming a test circuit over the semiconductor substrate, the test circuit comprising first and second sets of interconnects electrically connected to the device regions and the device gate structures, respectively;
conducting a test with the test circuit; and
removing, through an etching or planarization procedure, the first and second sets of interconnects after conducting the test;
wherein:
forming the test circuit comprises depositing a conductive material to form the first and second sets of interconnects;
depositing the conductive material also forms contact plugs that establish a respective contact to each device region and each device gate structure;
removing the first and second sets of interconnects does not remove the contact plugs;
the device gate structures comprise first and second gate structures;
the first and second gate structures comprise first and second gate oxide layers, respectively;
the first and second gate oxide layers have different thicknesses; and
conducting the test comprises:
applying a first stress voltage to the first gate structure via a first interconnect of the second set of interconnects; and
applying a second gate stress voltage to the second gate structure via a second interconnect of the second set of interconnects.
12. The method of claim 11 , further comprising conducting metallization of the semiconductor device after removing the first and second sets of interconnects.
13. The method of claim 11 , wherein removing the first and second sets of interconnects comprises implementing a wafer planarization process.
14. The method of claim 11 , wherein forming the device regions comprises conducting an implantation of dopant into the semiconductor substrate, the dopant implantation being configured to define a cross-under connector of the test circuit.
15. The method of claim 11 , wherein forming the device regions comprises conducting an implantation of dopant into the semiconductor substrate, the dopant implantation being configured to define a resistor of the test circuit.
16. A method of fabricating a semiconductor device, the method comprising:
forming device regions in a semiconductor substrate;
forming device gate structures on the semiconductor substrate;
depositing a dielectric layer over the semiconductor substrate;
patterning the dielectric layer to define contact openings for the device regions and the device gate structures;
forming a test circuit over the semiconductor substrate, the test circuit comprising first and second sets of interconnects electrically connected to the device regions and the device gate structures, respectively;
conducting a test with the test circuit; and
removing the first and second sets of interconnects after conducting the test;
wherein forming the test circuit comprises:
depositing metal in the contact openings to form contact plugs and on the dielectric layer to form the first and second sets of interconnects; and
patterning the metal on the dielectric layer to define the first and second sets of interconnects.
17. A semiconductor wafer comprising:
a semiconductor substrate in which device regions of a plurality of semiconductor devices are disposed;
first and second sets of device gate structures of the plurality of semiconductor devices, the first and second sets of device gate structures being supported by the semiconductor substrate; and
a test circuit supported by the semiconductor substrate and comprising:
a plurality of sacrificial interconnects electrically connected to the device regions and the first and second sets of device gate structures;
a first probe pad electrically connected to the first set of device gate structures by a first network of the plurality of sacrificial interconnects;
a second probe pad electrically connected to the second set of device gate structures by a second network of the plurality of sacrificial interconnects; and
a third probe pad electrically connected to the device regions by a third network of the plurality of sacrificial interconnects;
wherein:
each device gate structure of the first set of device gate structures comprises a respective first gate oxide layer;
each device gate structure of the second set of device gate structures comprises a respective second gate oxide layer;
the first and second gate oxide layers have different thicknesses.
18. The semiconductor wafer of claim 17 , wherein:
the first network comprises a serpentine interconnect that electrically connects the first set of device gate structures to the first probe pad; and
the test circuit further comprises a fourth probe pad electrically connected to the first set of device gate structures by a return interconnect of the plurality of sacrificial interconnects.
19. The semiconductor wafer of claim 17 , wherein one of the plurality of sacrificial interconnects extends across a die boundary.