Method and device for generating floating-point values
View Patent ↗A floating-point value can represent a number or something that is not a number (NaN). A floating-point value that is a NaN includes a portion that stores information about the source operands of the instruction.
1. A method comprising:
receiving a first instruction having a plurality of operands at an execution unit circuitry of a data processor; and
in response to execution of the first instruction at the execution unit circuitry, generating a propagated first NaN resultant for the first instruction, the first NaN resultant comprising a first NaN source indicator that indicates the resultant is a propagated NaN.
2. The method of claim 1 , wherein the first NaN source indicator is located at a predefined location of the first NaN resultant.
3. The method of claim 1 , wherein the first NaN source indicator further identifies a source location of a source operand.
4. The method of claim 3 , wherein the source location is a general purpose register.
5. The method of claim 1 , wherein the first NaN source indicator further identifies which operands of the plurality of operands were NaNs.
6. The method of claim 1 , wherein the first NaN source indicator includes a plurality of mapped bits including a first mapped bit and a second mapped bit, a first operand of the first instruction mapped to the first mapped bit of the plurality of mapped bits, a second operand of the first instruction mapped to the second mapped bit of the plurality of mapped bits; the method further comprising:
asserting each mapped bit of the plurality of mapped bits in response to its respective operand being a NaN.
7. The method of claim 1 , further comprising:
receiving a second instruction having a plurality of operands at the execution unit circuitry; and
in response to execution of the second instruction at the execution unit circuitry, generating a non-propagated second NaN resultant for the second instruction, the second NaN resultant comprising a second NaN source indicator that indicates the NaN resultant was not propagated.
8. The method of claim 1 , wherein the first NaN source indicator comprises a plurality of bits corresponds to a first operand of the instruction, and, in response to the first operand being a NaN, the first NaN source indicator indicates that the first operand is the NaN; the first NaN resultant further comprises a second NaN source indicator that comprises a plurality of bits, and that corresponds to a second operand of the instruction, and, in response to the second operand being a NaN, the second NaN source indicator indicates that the second operand is the NaN.
9. The method of claim 8 , wherein the first NaN source indicator further identifies a source location of the first operand in response to the first being a NaN.
10. The method of claim 1 , wherein the first NaN source indicator corresponds to a first operand of the instruction, and, in response to the first operand being a NaN, the first NaN source indicator indicates that the first operand is a NaN and indicates a source location of the first operand; the first NaN resultant further comprises a second NaN source indicator that corresponds to a second operand of the instruction, and, in response to the second operand being a non-NaN, the second NaN source indicator indicates that the second operand is a non-NaN.
11. The method of claim 1 , wherein the first NaN source indicator corresponds to a first operand of the instruction, and, in response to the first operand being a non-NaN, the first NaN source indicator indicates that the first operand is a non-NaN; the first NaN resultant further comprises a second NaN source indicator that corresponds to a second operand of the instruction, and, in response to the second operand being a non-NaN, the second NaN source indicator indicates that the second operand is a non-NaN.
12. The method of claim 1 further comprising:
receiving a second instruction having a plurality of operands at the execution unit circuitry, and
in response to execution of the second instruction at the execution unit circuitry, generating a propagated second NaN resultant for the second instruction, the second NaN resultant comprising a second NaN source indicator that indicates the resultant is not a propagated NaN.
13. A processing device comprising:
instruction fetch circuitry of a data processor core to fetch a floating-point instruction having a plurality of operands; and
execution unit circuitry of the data processor core to execute the instruction to determine a resultant, in response to the resultant being a NaN resultant, the execution unit circuitry to determine whether the NaN resultant was propagated from an operand, and, in response to determining that the NaN resultant was propagated from the operand, the execution unit circuitry is to store a first NaN source indicator that indicates the NaN resultant is a propagated NaN.
14. The processing device of claim 13 , wherein the first NaN source indicator is stored at a predetermined location of the NaN resultant.
15. The processing device of claim 13 , wherein the first NaN source indicator further identifies a source location of an operand of the plurality of operands that was propagated.
16. The device of claim 15 , wherein each one of the plurality of operands is stored at a respective register that is identified by the instruction.
17. The device of claim 13 , wherein the first NaN source indicator further identifies an operand of the plurality of operands that is a NaN operand.
18. The device of claim 13 , wherein the NaN source indicator includes a plurality of mapped bits, each bit of the plurality of mapped bits mapped to a corresponding operand of the instruction, wherein the execution unit circuitry is to assert each bit of the plurality of mapped bits that is mapped to a NaN operand.
19. The device of claim 13 , wherein in response to the execution unit circuitry determining that the NaN resultant is not propagated, the execution unit circuitry is to store a second NaN source indicator that indicates the NaN resultant was not propagated.
20. A method comprising:
receiving a first instruction having a plurality of operands at execution unit circuitry of a data processor;
fetching a NaN operand comprising a first NaN source indicator having a plurality of mapped bits, and a second NaN source indicator having a plurality of mapped bits; and
generating a propagated NaN resultant comprising a third NaN source indicator having a plurality of bits, and a fourth NaN source indicator having a plurality of bits, wherein a portion of the third NaN source indicator is based upon a portion of the first NaN source indicator, and a portion of the fourth NaN source indicator is based upon a portion of the second NaN source indicator.