Granted Patent B1

US 8,901,721 · App. 13/972,885 · Granted Dec 2, 2014

Abstract

Claims (31)

1. A semiconductor die package, comprising:

a die pad;

a first set of lead fingers that are spaced from and project outwardly from the die pad, wherein the lead fingers have proximal ends close to the die pad and distal ends spaced from the die pad;

a second set of lead fingers that are spaced from and project outwardly from the die pad, wherein the second set of lead fingers have proximal ends close to the die pad and distal ends spaced from the die pad,

a semiconductor die attached to the die pad, wherein bonding pads on the semiconductor die are selectively electrically coupled to the proximal ends of the first and second sets of lead fingers with bond wires; and

an encapsulation material covering the bond wires, the semiconductor die and the proximal ends of the first and second sets of lead fingers, wherein the encapsulating material forms a housing with edges from which the first and second sets of lead fingers extend, the housing having an underside that has a least one slot formed therein and wherein the distal ends of the first set of lead fingers are located away from the housing and the distal ends of the second set of lead fingers are located at least partially in the slot.

2. The semiconductor die package of claim 1 , wherein the first and second sets of lead fingers are interleaved.

3. The semiconductor die package of claim 2 , wherein members of the first set of lead fingers are in an alternating arrangement with members of the second set of lead fingers.

4. The semiconductor die package of claim 1 , wherein each lead of the second set of lead fingers is located in the slot.

5. The semiconductor die package of claim 4 , wherein the distal end of at least one of the lead fingers is located in the slot.

6. The semiconductor die package of claim 4 , wherein there is more than one said slot and each slot has the distal end of one of the lead fingers located therein.

7. The semiconductor die package of claim 6 , wherein respective edges of the housing include a recess, and a mid-region of each of the leads of the second set of lead fingers is located in a respective one of the recesses.

8. The semiconductor die package of claim 6 , wherein each of the recesses is aligned with a respective said slot to thereby provide channels for the second set of lead fingers.

9. The semiconductor die package of claim 1 , wherein each one of the second set of lead fingers is bent to have a first region extending out of the housing, an upright mid-region, and the distal end that is located in the slot.

10. A method of packaging a semiconductor die, comprising the steps of:

providing an electrically conductive lead frame with a least one die pad, a frame member surrounding the die pad and a plurality of lead fingers attached to the frame member and disposed between the frame member and die pad such that each of the lead fingers has a proximal end near the die pad and a distal end located away from the die pad;

attaching a semiconductor die to the die pad;

electrically coupling contact pads on the semiconductor die with respective proximal ends of the lead fingers;

encapsulating at least the die, the die pad and the proximal ends of the lead fingers with an encapsulation material, the encapsulation material forming a housing with edges from which the lead fingers extend, the housing having an underside that has a least one slot therein;

detaching the lead fingers from the frame member; and

bending the lead fingers into a first and second sets of lead fingers, wherein the distal ends of the first set of lead fingers are located away from the housing and the distal ends of the second set of lead fingers are located at least partially in the slot.

11. The method of packaging a semiconductor die of claim 10 , wherein the detaching step includes separating the lead fingers from each other.

12. The method of packaging a semiconductor die of claim 10 , wherein the first and second sets of lead fingers are interleaved in an alternating arrangement.

13. The method of packaging a semiconductor die of claim 10 , wherein the distal end of each lead finger of the second set of lead fingers is located in the slot.

14. The method of packaging a semiconductor die of claim 10 , wherein the distal end of at least one of the lead fingers is located in the slot.

15. The method of packaging a semiconductor die of claim 10 , wherein there is more than one said slot and each slot has the distal end of one of the lead fingers located therein.

16. The method of packaging a semiconductor die of claim 15 , wherein there is a plurality of recesses in a respective edge of the housing, and an upright mid-region of each of the leads of the second set of lead fingers is located in a respective one of the recesses.

17. The method of packaging a semiconductor die of claim 16 , wherein each of the recesses is aligned with a respective said slot to thereby provide channels for the second set of lead fingers.

18. The method of packaging a semiconductor die of claim 16 , wherein each of the lead fingers of the second set of lead fingers has a first region extending out of the housing and into a respective one of the recesses, the upright mid-region located in the respective one of the recesses, and the distal end located in the slot.

19. The method of packaging a semiconductor die of claim 10 , wherein each member of the second set of lead fingers is shorter than each member of the first set of lead fingers.

20. The method of packaging a semiconductor die of claim 10 , wherein the distal ends of the second set of lead fingers are spaced from the frame member.

Assignments (10)