Method of forming different voltage devices with high-K metal gate
View Patent ↗A method and apparatus are described for integrating high voltage (HV) transistor devices and medium voltage or dual gate oxide (DGO) transistor devices with low voltage (LV) core transistor devices on a single substrate, where each high voltage transistor device ( 160 ) includes a metal gate ( 124 ), an upper high-k gate dielectric layer ( 120 ), a middle gate dielectric layer ( 114 ) formed with a relatively lower high-k dual gate oxide layer, and a lower high voltage gate dielectric stack ( 108, 110 ) formed with one or more low-k gate oxide layers ( 22 ), where each DGO transistor device ( 161 ) includes a metal gate ( 124 ), an upper high-k gate dielectric layer ( 120 ), and a middle gate dielectric layer ( 114 ) formed with a relatively lower high-k dual gate oxide layer, and where each core transistor device ( 162 ) includes a metal gate ( 124 ), an upper high-k gate dielectric layer ( 120 ), and a base oxide layer ( 118 ) formed with one or more low-k gate oxide layers.
1. A semiconductor fabrication process comprising:
providing a wafer comprising a first device area for forming one or more first voltage level transistors, a second device area for forming one or more second voltage level dual gate oxide transistors, and a third device area for forming one or more third voltage level transistors;
forming a high voltage gate dielectric stack on the first and third device areas of the wafer and not on the second device area of the wafer;
forming a dual gate oxide layer over the first, second, and third device areas of the wafer by depositing one or more oxide layers on the high voltage gate dielectric stack and on the exposed second device area of the wafer;
removing the high voltage gate dielectric stack and dual gate oxide layer from the third device area of the wafer while leaving the dual gate oxide layer formed on the first and second device areas;
forming a high-k gate dielectric stack over the first, second, and third device areas of the wafer to cover the dual gate oxide layer formed on the first and second device areas and the third device area of the wafer; and
forming a plurality of patterned high-k metal gate electrodes on the high-k gate dielectric stack in each of the first, second, and third device areas; where the first voltage level is higher than the second voltage level which is higher than the third voltage level.
2. The semiconductor fabrication process of claim 1 , where providing the wafer comprises providing a first semiconductor layer as a semiconductor-on-insulator (SOI) substrate structure or bulk substrate structure comprising one or more shallow trench isolation regions for separating the first, second, and third device areas from one another.
3. The semiconductor fabrication process of claim 1 , where providing the wafer comprises providing a compressive silicon germanium layer formed in the second device area and in a portion of the third device area where PMOS transistors are formed.
4. The semiconductor fabrication process of claim 1 , where forming the high voltage gate dielectric stack comprises:
thermally growing a first oxide layer on the wafer on the first, second, and third device areas;
depositing a second oxide layer on the first oxide layer over the first, second, and third device areas; and
selectively removing the first and second oxide layers from the second device area, thereby exposing the second device area of the wafer.
5. The semiconductor fabrication process of claim 1 , where forming the dual gate oxide layer comprises depositing a high-k dielectric layer comprising a silicate or metal oxy-nitride material.
6. The semiconductor fabrication process of claim 1 , where removing the high voltage gate dielectric stack and dual gate oxide layer from the third device area comprises:
forming a patterned etch mask to cover the high voltage gate dielectric stack and dual gate oxide layer formed over the first device area and to protect the dual gate oxide layer formed over the second device area; and
selectively etching the high voltage gate dielectric stack and dual gate oxide layer formed over the third device area to expose the third device area.
7. The semiconductor fabrication process of claim 1 , where forming the high-k gate dielectric stack comprises:
thermally growing a base oxide layer on the wafer on at least the exposed third device area of the wafer;
depositing a high-k layer of hafnium-based dielectric material to cover the dual gate oxide layer formed over the first and second device areas and to cover the base oxide layer formed over the third device area; and
depositing a metal-based barrier layer on the high-k layer of hafnium-based dielectric material to cover the first, second, and third device areas.
8. The semiconductor fabrication process of claim 1 , where forming the plurality of patterned high-k metal gate electrodes comprises:
depositing a polysilicon layer on the high-k gate dielectric stack in each of the first, second, and third device areas; and
patterning and etching the polysilicon layer and underlying high-k gate dielectric stack to form the plurality of patterned high-k metal gate electrodes.