IP Library Granted Patent US 9,508,701
Granted Patent B2
US 9,508,701 · App. 14/039,622 · Granted Nov 29, 2016

3D device packaging using through-substrate pillars

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Quick Facts
Patent No.
US 9,508,701
App. No.
14/039,622
Granted
Nov 29, 2016
Kind
B2
Abstract

A method for 3D device packaging utilizes through-substrate pillars to mechanically and electrically bond two or more dice. The first die includes a set of access holes extending from a surface of the first die to a set of pads at a metal layer of the first die. The second die includes a set of metal pillars. The first die and the second die are stacked such that each metal pillar extends from a surface of the second die to a corresponding pad via a corresponding access hole. The first die and second die are mechanically and electrically bonded via solder joints formed between the metal pillars and the corresponding pads.

Claims (49)

1. A method comprising:

stacking a first semiconductor die with a second semiconductor die, the first semiconductor die comprising a first set of access holes extending from a first surface of the first semiconductor die to a first set of pads at a metal layer of the first semiconductor die and the second semiconductor die comprising a first set of metal pillars, each metal pillar of the first set of metal pillars extending from a surface of the second semiconductor die to a first surface of a corresponding pad of the first set of pads via a corresponding access hole of the first set of access holes; and

bonding the first semiconductor die and the second semiconductor die such that the metal pillars of the first set of metal pillars are in electrical contact with the corresponding pads of the first set of pads.

2. The method of claim 1 , further comprising:

encapsulating the first semiconductor die with an encapsulating material; and

forming a set of pad openings, each pad opening of the set of pad openings extending from a surface of the encapsulating material to a second surface of a corresponding pad of the first set of pads.

3. The method of claim 2 , further comprising:

forming a wire bond with a pad of the first set of pads via a corresponding pad opening of the set of pad openings.

4. The method of claim 1 , further comprising:

performing a solder reflow to form solder joints coupling the metal pillars of the first set of metal pillars with the corresponding pads of the first set of pads.

5. The method of claim 1 , further comprising:

stacking a third semiconductor die with the first semiconductor die, the third semiconductor die comprising a second set of access holes extending from a surface of the third semiconductor die to a second set of pads at a metal layer of the third semiconductor die and the first semiconductor die comprising a second set of metal pillars, each metal pillar of the second set of metal pillars extending from a second surface of the first semiconductor die to a surface of a corresponding pad of the second set of pads via a corresponding access hole of the second set of access holes.

6. A method comprising:

forming a first set of pads at a metal layer of a first semiconductor die;

forming a set of access holes in a first arrangement at the first semiconductor die, each access hole of the set of access holes extending from a surface of the first semiconductor die to a corresponding pad of the set of pads; and

bonding the first semiconductor die to a second semiconductor die, the second semiconductor die comprising a set of metal pillars disposed at a surface of the second semiconductor die in a second arrangement corresponding to the first arrangement, the set of metal pillars extending into the first semiconductor die via the set of access holes such that each metal pillar of the set of metal pillars contacts a first surface of a corresponding pad of the set of pads.

7. The method of claim 6 , wherein bonding the first semiconductor die to the second semiconductor die comprises:

performing a solder reflow to form solder joints coupling the metal pillars with the corresponding pads.

8. The method of claim 6 , wherein the first surface of the first semiconductor die is characterized as a backside of the first semiconductor die.

9. The method of claim 6 , wherein forming the set of access holes comprises:

forming, at each access hole of the set of access holes, a concave surface at the first surface of the corresponding pad.

10. The method of claim 6 , wherein forming the set of access holes comprises forming the set of access holes with walls substantially perpendicular to the surface of the first semiconductor die.

11. The method of claim 6 , further comprising:

encapsulating the first semiconductor die with an encapsulating material; and

forming a set of pad openings, each pad opening of the set of pad openings extending from a surface of the encapsulating material to a second surface of a corresponding pad of the set of pads.

12. The method of claim 11 , further comprising:

forming a wire bond with the second surface of a pad of the set of pads via a corresponding pad opening of the set of pad openings.

13. The method of claim 6 , wherein the metal layer comprises a surface metal layer of the first semiconductor die.

14. A device package comprising:

a first semiconductor die comprising:

a first metal layer comprising a first set of pads; and

a set of access holes in a first arrangement, each access hole of the set of access holes extending from a first surface of the first semiconductor die to a first surface of a corresponding pad of the first set of pads; and

a second semiconductor die bonded to the first semiconductor die, the second semiconductor die comprising:

a first set of metal pillars disposed in a second arrangement corresponding to the first arrangement at a surface of the second semiconductor die that faces the surface of the first semiconductor die, each metal pillar of the first set of metal pillars extending to and in contact with the first surface of a corresponding pad of the set of pads via a corresponding access hole of the set of access holes.

15. The device of claim 14 , wherein each metal pillar of the set of metal pillars is electrically and mechanically coupled to the corresponding pad via a solder joint.

16. The device of claim 14 , wherein at least one access hole of the set of access holes comprises a concave surface at least partially formed at the first surface of the corresponding pad of the set of pads.

17. The device of claim 14 , further comprising:

an encapsulating material encapsulating the first semiconductor die; and

a set of pad openings formed through the encapsulating material to a second surface of a pad of the set of pads.

18. The device of claim 17 , further comprising:

a wire bond disposed in at least one pad opening of the set of pad openings at the second surface of the pad.

19. The device of claim 14 , wherein the first surface of the first semiconductor die is characterized as a backside of the first semiconductor die.

20. The device of claim 14 , wherein:

the first semiconductor die further comprises:

a second set of metal pillars disposed in a third arrangement at a second surface of the first semiconductor die; and

the device package further comprises:

a third semiconductor die bonded to the first semiconductor die, the third semiconductor die comprising:

a second metal layer comprising a second set of pads; and

a second set of access holes in a fourth arrangement corresponding to the third arrangement, each access hole of the second set of access holes extending from a surface of the third semiconductor die that faces the second surface of the first semiconductor die to a surface of a corresponding pad of the second set of pads such that each metal pillar of the second set of metal pillars extends, via a corresponding access hole of the second set of access holes, to and in contact with the surface of the corresponding pad of the second set of pads.

Assignments (29)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNMENT DOCUMENTATION - INITIAL CONVENYANCE LISTED CHANGE OF NAME. PREVIOUSLY RECORDED ON REEL 040579 FRAME 0827. ASSIGNOR(S) HEREBY CONFIRMS THE UPDATE CONVEYANCE TO MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Dec 15, 2016
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 040945/0252 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
CHANGE OF NAME Recorded Nov 9, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040579/0827 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PCT NUMBERS IB2013000664, US2013051970, US201305935 PREVIOUSLY RECORDED AT REEL: 037444 FRAME: 0787. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Oct 17, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 040450/0715 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0787 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0874 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 13, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 031627/0158 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 13, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031627/0201 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 27, 2013
From: REBER, DOUGLAS M.; SHROFF, MEHUL D.; TRAVIS, EDWARD O.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 031305/0661 →