Amplifiers and related integrated circuits
View Patent ↗Apparatus are provided for amplifier systems and related integrated circuits are provided. An exemplary integrated circuit includes a main amplifier arrangement, first impedance matching circuitry coupled between the output of the main amplifier arrangement and a first output of the integrated circuit, a peaking amplifier arrangement, and second impedance matching circuitry coupled between the output of the peaking amplifier arrangement and a second output of the integrated circuit. In one exemplary embodiment, the first impedance matching circuitry and the second impedance matching circuitry have different circuit topologies and different physical topologies.
1. A circuit comprising:
a first amplifier arrangement having a first amplifier output;
first impedance matching circuitry coupled between the first amplifier output and a first output of the circuit, wherein the first impedance matching circuitry comprises a high-pass impedance matching circuit topology;
a second amplifier arrangement having a second amplifier output; and
second impedance matching circuitry coupled between the second amplifier output and a second output of the circuit, wherein a topology of the second impedance matching circuitry and a topology of the first impedance matching circuitry are different, and wherein the second impedance matching circuitry comprises a low-pass impedance matching circuit topology, and wherein the first impedance matching circuitry causes a phase of the signal at the first output of the integrated circuit to be shifted by 90 degrees relative to the signal at the first amplifier output, and the second impedance matching circuitry causes a phase of the signal at the second output of the integrated circuit to be shifted by 180 degrees relative to the signal at the second amplifier output.
2. A circuit comprising:
a first amplifier arrangement having a first amplifier output, wherein the first amplifier arrangement is configured to operate in Class AB mode;
first impedance matching circuitry coupled between the first amplifier output and a first output of the circuit, wherein the first impedance matching circuitry comprises a high-pass impedance matching circuit topology;
a second amplifier arrangement having a second amplifier output, wherein the second amplifier arrangement is configured to operate in Class C mode; and
second impedance matching circuitry coupled between the second amplifier output and a second output of the circuit, wherein a topology of the second impedance matching circuitry and a topology of the first impedance matching circuitry are different, and wherein the second impedance matching circuitry comprises a low-pass impedance matching circuit topology, and wherein a phase inversion provided by the first impedance matching circuitry and a phase inversion provided by the second impedance matching circuitry are different.
3. The circuit of claim 2 , wherein the first impedance matching circuitry provides a single phase inversion and the second impedance matching circuitry provides a double phase inversion.
4. The circuit of claim 2 , wherein a physical topology of the second impedance matching circuitry and a physical topology of the first impedance matching circuitry are different.
5. A circuit comprising:
a first amplifier arrangement having a first amplifier output;
first impedance matching circuitry coupled between the first amplifier output and a first output of the circuit, wherein the first impedance matching circuitry comprises a high-pass impedance matching circuit topology, wherein the first impedance matching circuitry causes a phase of the si nal at an output of the first impedance matching circuitry to be shifted by 90 degrees relative to the signal at the output of the first amplifier arrangement, and wherein the first impedance matching circuitry comprises:
a first inductive element coupled between a first node and the first output, the first node being coupled to the first amplifier output,
a second inductive element coupled to the first node, and
a first capacitive element coupled between the second inductive element and a ground reference voltage node, such that the second inductive element and the first capacitive element are configured electrically in series between the first node and the ground reference voltage node;
a second amplifier arrangement having a second amplifier output; and
second impedance matching circuitry coupled between the second amplifier output and a second output of the circuit, wherein a topology of the second impedance matching circuitry and a topology of the first impedance matching circuitry are different, and wherein the second impedance matching circuitry comprises a low-pass impedance matching circuit topology, and wherein the second impedance matching circuitry causes a phase of the signal at an output of the second impedance matching circuitry to be shifted by 180 degrees relative to the signal at the output of the second amplifier arrangement, wherein the second impedance matching circuitry comprises:
a third inductive element coupled between the second amplifier output and a second node,
a fourth inductive element coupled between the second node and the second output, and
a second capacitive element coupled between the second node and the ground reference voltage node.
6. A circuit comprising:
a first amplifier arrangement having a first amplifier output, wherein the first amplifier arrangement comprises a first transistor configured to operate in Class AB mode;
first impedance matching circuitry coupled between the first amplifier output and a first output of the circuit, wherein the first impedance matching circuitry comprises a high-pass impedance matching circuit topology, wherein the first impedance matching circuitry comprises:
a first inductive element coupled between a first node and the first output, the first node being coupled to the first amplifier output,
a second inductive element coupled to the first node, and
a first capacitive element coupled between the second inductive element and a ground reference voltage node, such that the second inductive element and the first capacitive element are configured electrically in series between the first node and the ground reference voltage node;
a second amplifier arrangement having a second amplifier output, wherein the second amplifier arrangement comprises a second transistor configured to operate in Class C mode; and
second impedance matching circuitry coupled between the second amplifier output and a second output of the circuit, wherein a topology of the second impedance matching circuitry and a topology of the first impedance matching circuitry are different, and wherein the second impedance matching circuitry comprises a low-pass impedance matching circuit topology, and wherein a phase inversion provided by the first impedance matching circuitry and a phase inversion provided by the second impedance matching circuitry are different, wherein the second impedance matching circuitry comprises:
a third inductive element coupled between the second amplifier output and a second node,
a fourth inductive element coupled between the second node and the second output, and
a second capacitive element coupled between the second node and the around reference voltage node.
7. The circuit of claim 6 , wherein:
the first inductive element comprises a first wire connected between the first amplifier arrangement and the first output;
the second inductive element comprises a second wire connected between the first amplifier arrangement and the first capacitive element;
the third inductive element comprises a third wire connected between the second amplifier arrangement and the second capacitive element; and
the fourth inductive element comprises a fourth wire connected between the second capacitive element and the second output.
8. The circuit of claim 7 , further comprising a metal substrate configured to provide the ground reference voltage node, wherein:
the first capacitive element and the second capacitive element are each disposed on the metal substrate;
the first amplifier arrangement comprises a first transistor disposed on the metal substrate, the first transistor including a first contact region for the first amplifier output;
the first wire is connected between the first contact region and the first output;
the second wire is connected between the first contact region and the first capacitive element;
the second amplifier arrangement comprises a second transistor mounted on the metal substrate, the second transistor including a second contact region for the second amplifier output; and
the third inductive element is connected between the second contact region and the second capacitive element.
9. The circuit of claim 7 , wherein a trajectory of the second wire is oblique to a trajectory of the third wire.
10. A circuit comprising:
a first node;
a second node;
a first amplifier configured to operate in Class AB mode;
a second amplifier configured to operate in Class C mode;
first impedance matching circuitry coupled between an output of the first amplifier and the first node, the first impedance matching circuitry being configured as a shunt inductance impedance matching circuit, and wherein the first impedance matching circuitry causes a phase of the signal at an output of the first impedance matching circuitry to be shifted by 90 degrees relative to the signal at the output of the first amplifier; and
second impedance matching circuitry coupled between an output of the second amplifier and the second node, the second impedance matching circuitry being configured as a shunt capacitance impedance matching circuit, and wherein the second impedance matching circuitry causes a phase of the signal at an output of the second impedance matching circuitry to be shifted by 180 degrees relative to the signal at the output of the second amplifier.
11. The circuit of claim 10 , wherein:
the first amplifier comprises one or more transistors formed on a first die;
the second amplifier comprises one or more transistors formed on a second die; and
a width of the second die is greater than a width of the first die.
12. A circuit comprising:
a first node;
a second node;
a first amplifier configured to operate in Class AB mode;
a second amplifier configured to operate in Class C mode;
first impedance matching circuitry coupled between an output of the first amplifier and the first node, the first impedance matching circuitry being configured as a shunt inductance impedance matching circuit, wherein the first impedance matching circuitry comprises:
a first inductive element connected between the output of the first amplifier and the first node, and
a second inductive element connected between the output of the first amplifier and a first reference voltage node; and
second impedance matching circuitry coupled between an output of the second amplifier and the second node, the second impedance matching circuitry being configured as a shunt capacitance impedance matching circuit, wherein the second impedance matching circuitry comprises:
a first capacitive element electrically connected to a ground reference voltage node for the circuit,
a third inductive element connected between the output of the second amplifier and the second capacitive element, and
a fourth inductive element connected between the second capacitive element and the second node.
13. The circuit of claim 12 , wherein the first impedance matching circuitry further comprises a second capacitive element coupled between the first reference voltage node and the ground reference voltage node.
14. The circuit of claim 13 , wherein a capacitance of the second capacitive element is configured to provide a virtual ground reference voltage for radio frequency signals at the output of the first amplifier at the first reference voltage node.
15. The circuit of claim 13 , wherein:
the second inductive element comprises a first conductive wire having a first trajectory in a first direction;
the third inductive element comprises a second conductive wire having a second trajectory in the first direction; and
a cross-section of the first trajectory along the first direction is different from a cross-section of the second trajectory along the first direction.
16. An amplifier system comprising:
a main amplifier arrangement configured for a first class of operation;
a peaking amplifier arrangement configured for a second class of operation that is different than the first class of operation;
high-pass impedance matching circuitry coupled to an output of the main amplifier arrangement, wherein the high-pass impedance matching circuitry causes a phase of the signal at an output of the high-pass impedance matching circuitry to be shifted by 90 degrees relative to the signal at the output of the main amplifier arrangement; and
low-pass impedance matching circuitry coupled to an output of the peaking amplifier arrangement, wherein the low-pass impedance matching circuitry causes a phase of the signal at an output of the low-pass impedance matching circuitry to be shifted by 180 degrees relative to the signal at the output of the peaking amplifier arrangement.
17. The amplifier system of claim 16 , further comprising:
a power combiner having a first input and a second input; and
a first impedance transforming element coupled between the first input and the first impedance matching circuitry, the second input being coupled to the second impedance matching circuitry.
18. The amplifier system of claim 17 , further comprising:
a power splitter having a first output and a second output;
a first impedance matching element coupled between the second output and the peaking amplifier arrangement, the first impedance matching element including a quarter wave transformer, wherein the first output is coupled to the main amplifier arrangement.