System and method for enabling maximum performance operation within an extended ambient temperature range
A system method of initializing operation of a semiconductor device including detecting de-assertion of an external reset signal while the semiconductor device in a reset state, monitoring a temperature level of the semiconductor device, and while the temperature level is below a predetermined minimum operating temperature level that allows the semiconductor device to operate at a maximum performance level, keeping the semiconductor device in the reset state and asserting at least one operating parameter on the semiconductor device at an elevated level to generate heat on the semiconductor device, and releasing the reset condition when the temperature level is at least the predetermined minimum operating temperature level. The operating parameter may be clock frequency or supply voltage level or a combination of both. Different elevated clock frequencies and/or different minimum operating temperature levels are contemplated. Additionally turning off an external cooling system during the heating process is contemplated.
1. A method of initializing operation of a semiconductor device, comprising:
detecting de-assertion of an external reset signal while the semiconductor device is in a reset condition;
monitoring a temperature level of the semiconductor device;
while the temperature level is below a predetermined minimum operating temperature level that allows the semiconductor device to operate at a maximum performance level,
keeping the semiconductor device in the reset condition; and
asserting a clock signal to a high frequency block incorporating at least one clock tree on the semiconductor device at an elevated frequency level to generate resistive heat on the semiconductor device while receiving the clock signal; and
releasing the reset condition when the temperature level is at least the predetermined minimum operating temperature level.
2. The method of claim 1 , wherein the clock signal is provided to a high frequency block of the semiconductor device that is unable to operate at the maximum performance level while the temperature level is below the predetermined minimum operating temperature level and the clock signal is at the elevated frequency level.
3. The method of claim 1 , wherein said asserting a clock signal comprises asserting a clock signal at a maximum frequency level of a frequency generator of the semiconductor device.
4. The method of claim 1 , further comprising commanding a supply voltage provided to the semiconductor device to be greater than a predetermined normal operating voltage level.
5. The method of claim 1 , further comprising commanding a supply voltage provided to the semiconductor device to be asserted at a maximum voltage level tolerable by the semiconductor device.
6. The method of claim 1 , wherein said monitoring a temperature level comprises measuring a plurality of temperatures at a plurality of locations on the semiconductor device, and wherein said releasing the reset condition comprises releasing the reset condition when a minimum one of the plurality of temperatures is at least the predetermined minimum operating temperature level.
7. The method of claim 1 , wherein said monitoring a temperature level comprises measuring a plurality of temperature levels at a corresponding plurality of locations of the semiconductor device, wherein each of the plurality of locations of the semiconductor device has a corresponding one of a plurality of minimum operating temperature levels, and wherein said releasing the reset condition comprises releasing the reset condition when a temperature level of each of the plurality of locations has reached a corresponding one of the plurality of minimum operating temperature levels.
8. The method of claim 1 , further comprising commanding that an external cooling system be turned off while the semiconductor device is in the reset condition.
9. A semiconductor device, comprising:
a thermal monitor that monitors a temperature of the semiconductor device and that provides a temperature value indicative thereof;
a frequency control block that asserts a clock signal;
a high frequency block incorporating at least one clock tree that generates resistive heating while receiving said clock signal;
sequence logic that, in response to an external reset signal being de-asserted when said temperature value indicates that the temperature is below a predetermined minimum operating temperature level, commands said frequency control block to assert said clock signal at an elevated frequency level to generate heat on the semiconductor device while maintaining an internal reset state; and
wherein said sequence logic releases said reset state to allow the semiconductor device to operate at a maximum performance level when said temperature value indicates that the temperature is at least said predetermined minimum operating temperature level.
10. The semiconductor device of claim 9 , wherein said clock signal is provided to a high frequency block of the semiconductor device that is unable to operate at said maximum performance level while the temperature is below said predetermined minimum operating temperature level and said clock signal is at the elevated frequency level.
11. The semiconductor device of claim 9 , further comprising:
a voltage control block that asserts a supply voltage request signal; and
wherein said sequence logic commands said voltage control block to request a supply voltage provided to the semiconductor device to be at an elevated voltage level.
12. The semiconductor device of claim 9 , wherein said thermal monitor controls operation of an external cooling system, and wherein said sequence logic further commands said thermal monitor to turn off said external cooling system while said temperature value indicates that the temperature is below a predetermined minimum operating temperature level.
13. A method of initializing operation of a semiconductor device, comprising:
detecting de-assertion of an external reset signal while the semiconductor device is in a reset condition;
monitoring a temperature level of the semiconductor device;
while the temperature level is below a predetermined minimum operating temperature level that allows the semiconductor device to operate at a maximum performance level,
keeping the semiconductor device in the reset condition;
asserting a clock signal to a high frequency block incorporating at least one clock tree on the semiconductor device at an elevated frequency level to generate resistive heat on the semiconductor device while receiving the clock signal; and
commanding a supply voltage provided to the semiconductor device to be greater than a predetermined normal operating voltage level to generate heat on the semiconductor device; and
releasing the reset condition when the temperature level is at least the predetermined minimum operating temperature level.