IP Library Granted Patent US 9,159,682
Granted Patent B2
US 9,159,682 · App. 14/020,841 · Granted Oct 13, 2015

Copper pillar bump and flip chip package using same

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,159,682
App. No.
14/020,841
Granted
Oct 13, 2015
Kind
B2
Abstract

Electrically conductive pillars with a solder cap are formed on a substrate with an electroplating process. A flip-chip die having solder wettable pads is attached to the substrate with the conductive pillars contacting the solder wettable pads.

Claims (21)

1. A method of assembling a semiconductor device, comprising:

providing a substrate having a substrate body with an inner face having inner contact pads and an outer face having outer contact pads, and electrically conductive pillars that extend from the inner contact pads, wherein the step of providing the substrate includes:

providing a body of insulating material having the body inner and outer faces;

providing the substrate inner contact pads on the inner face of the substrate body;

providing the substrate outer contact pads on the outer face of the substrate body;

wherein the body of insulating material includes interconnectors embedded in the insulating material that interconnect the inner and outer contact pads;

providing a solder mask layer overlying the inner face of the substrate between the inner contact pads, wherein the solder mask layer has apertures over the inner contact pads that are narrower than the inner contact pads;

forming a resist layer covering the solder mask layer, the resist layer also having apertures over the inner contact pads, wherein a height of the resist layer is greater than a height of the solder mask layer;

forming the pillars through the solder mask layer on the inner contact pads within the apertures of the solder mask layer and the apertures of the resist layer;

forming solder caps on the remote ends of the pillars, wherein the solder caps are formed within the apertures of the resist layer; and

removing the resist layer such that after said removing, a height of exposed portions of the pillars is greater than a height of neck portions of the pillars embedded in the solder mask layer;

attaching an active face of a flip chip semiconductor die to the substrate inner face, wherein die bonding pads on the die active face receive the electrically conductive pillars; and

electrically connecting the pillars with the die bonding pads.

2. The method of assembling a semiconductor device of claim 1 , wherein the die bonding pads include a solder wettable layer.

3. The method of assembling a semiconductor device of claim 2 , wherein an exposed surface of the die bonding pads comprises an electro-less nickel with immersion gold coating.

4. The method of assembling a semiconductor device of claim 1 , wherein the step of electrically connecting the pillars with the die bonding pads includes performing a reflow process to connect the pillars to the die bonding pads.

5. The method of claim 1 , further comprising the step of attaching conductive balls to the substrate outer contact pads, wherein the conductive balls allow for connection of the semiconductor device to an external electrical device.

6. The method of claim 1 , wherein the pillars are formed of copper.

7. The method of claim 1 , wherein said apertures of the resist layer are wider than the apertures of the solder mask layer and the pillars have necks at the inner face into which extends the solder mask layer.

8. The method of claim 1 , wherein forming the pillars through the solder mask layer includes growing the pillars electrolytically within the apertures of the solder mask layer and the apertures of the resist layer.

9. The method of claim 8 , wherein forming the solder caps includes growing the solder caps electrolytically within said apertures of said resist layer.

Assignments (18)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PCT NUMBERS IB2013000664, US2013051970, US201305935 PREVIOUSLY RECORDED AT REEL: 037444 FRAME: 0787. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Oct 17, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 040450/0715 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0787 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0874 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 13, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 031627/0158 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 13, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031627/0201 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 8, 2013
From: FOONG, CHEE SENG; LOW, BOON YEW; KALANDAR, NAVAS KHAN ORATTI
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 031160/0300 →