INTEGRATED CIRCUIT DEVICES AND METHODS FOR SCHEDULING AND EXECUTING A RESTRICTED LOAD OPERATION
An integrated circuit device comprising at least one instruction processing module arranged to compare validation data with data stored within a target register upon receipt of a load validation instruction. Wherein, the instruction processing module is further arranged to proceed with execution of a next sequential instruction if the validation data matches the stored data within the target register, and to load the validation data into the target register if the validation data does not match the stored data within the target register.
1 . An integrated circuit device comprising:
at least one instruction processing module arranged to compare validation data with data stored within a target register upon receipt of a load validation instruction;
wherein the instruction processing module is further arranged to: proceed with execution of a next sequential instruction if the validation data matches the stored data within the target register, and load the validation data into the target register if the validation data does not match the stored data within the target register.
2 . The integrated circuit device of claim 1 wherein the at least one instruction processing module is further arranged to flush an instruction pipeline thereof if the validation data does not match the stored data.
3 . The integrated circuit device of claim 1 wherein the instruction processing module is arranged to disregard memory management error indications upon receipt of an initial load instruction.
4 . The integrated circuit device of claim 3 wherein the instruction processing module is arranged to disregard memory management error by blocking data reaching the target register.
5 . A method for executing a restricted load operation, the method comprising, within an instruction processing module:
receiving a load validation instruction; and
comparing validation data with data stored within a target register;
proceeding with execution of a next sequential instruction if the validation data matches the stored data within the target register; and
load the validation data into the target register if the validation data does not match the stored data within the target register.
6 . The method of claim 5 wherein the method further comprises flushing an instruction pipeline thereof if the validation data does not match the stored data.
7 . A method for scheduling a restricted load operation, the method comprising:
identifying at least one restricted load operation to be scheduled ahead of a scheduling restriction within an instruction sequence for execution by at least one instruction processing module;
inserting an initial load instruction for the restricted load operation ahead of the scheduling restriction within the instruction sequence; and inserting a load validation instruction into the instruction sequence after the scheduling restriction.
8 . The method of claim 7 wherein the load validation instruction is arranged to cause the instruction processing module to compare validation data with data stored within a target register and to:
proceed with execution of a next sequential instruction if the validation data matches the stored data within the target register; and
load the validation data into the target register if the validation data does not match the stored data within the target register.
9 . The method of claim 8 wherein the load validation instruction is further arranged to cause the instruction processing module to flush an instruction pipeline thereof if the validation data does not match the stored data.
10 . The method of claim 7 wherein the method further comprises inserting a data usage instruction into the instruction sequence after the initial load instruction and ahead of the scheduling restriction, the data usage instruction being arranged to cause the instruction processing module to use data stored within the target.
11 . The method of claim 10 wherein the method further comprises inserting a conditional jump instruction into the instruction sequence in parallel with or immediately following the load validation instruction, the conditional jump instruction being arranged to cause the instruction processing module to cause a change of flow to re-execute the speculatively scheduled usage instruction if the validation data does not match the stored data within the target register.
12 . The method of claim 7 wherein the initial load instruction is arranged to cause the instruction processing module to disregard memory management error.
13 . The integrated circuit device of claim 2 wherein the instruction processing module is arranged to disregard memory management error indications upon receipt of an initial load instruction.
14 . The method of claim 8 wherein the method further comprises inserting a data usage instruction into the instruction sequence after the initial load instruction and ahead of the scheduling restriction, the data usage instruction being arranged to cause the instruction processing module to use data stored within the target.
15 . The method of claim 9 wherein the method further comprises inserting a data usage instruction into the instruction sequence after the initial load instruction and ahead of the scheduling restriction, the data usage instruction being arranged to cause the instruction processing module to use data stored within the target.
16 . The method of claim 8 wherein the initial load instruction is arranged to cause the instruction processing module to disregard memory management error.
17 . The method of claim 9 wherein the initial load instruction is arranged to cause the instruction processing module to disregard memory management error.
18 . The method of claim 10 wherein the initial load instruction is arranged to cause the instruction processing module to disregard memory management error.
19 . The method of claim 11 wherein the initial load instruction is arranged to cause the instruction processing module to disregard memory management error.