Scheduling method and multi-core processor system
A scheduling method of a scheduler that manages threads is executed by a computer. The scheduling method includes selecting a CPU of relatively less load, when a second thread is generated from a first thread to be processed; determining whether the second thread operates exclusively from the first thread; copying a first storage area assessed by the first thread onto a second storage area managed by the CPU, when the second thread operates exclusively; calculating based on an address of the second storage area and a predetermined value, an offset for a second address for the second thread to access the first storage area; and notifying the CPU of the offset for the second address to convert a first address to a third address for accessing the second storage area.
1. A scheduling method of a scheduler configured to manage threads executed by a processor of a computer, the scheduling method comprising:
selecting a central processing unit (CPU) of relatively less load, when a second thread is generated from a first thread to be processed;
determining whether the second thread operates exclusively from the first thread;
copying a first storage area accessed by the first thread onto a second storage area managed by the CPU, when it is determined that the second thread operates exclusively;
generating a second thread context area in the first storage area, when it is determined that the second thread does not operate exclusively from the first thread;
calculating, based on an address of the second storage area and a predetermined value, an offset for a second address for the second thread to access the first storage area; and
notifying the offset for the second address to the CPU for converting a first address to a third address for accessing the second storage area.
2. The scheduling method according to claim 1 , further comprising accessing the second storage area, based on the third address, by the second thread.
3. The scheduling method according to claim 1 , wherein:
the calculating includes calculating an offset for the first address, based on an address of the first storage area and the predetermined value, and
the notifying includes notifying the CPU of the offset for the first address to convert, responsive to access of the second storage area and based on an offset to the first address and the predetermined value, the third address to a fourth address indicating the first storage area.
4. The scheduling method according to claim 1 , further comprising storing the first thread after the copying of the first storage area to the second storage area.
5. The scheduling method according to claim 1 , further comprising turning on a flag for synchronizing a cache memory, when the first thread does not operate exclusively.
6. The scheduling method according to claim 1 , further comprising turning off a flag for synchronizing a cache memory after the copying of the first storage area to the second storage area.
7. The scheduling method of according to claim 1 , further comprising reflecting, when the second thread is completed, an updated portion of the second storage area on the first storage area to recover the first thread.
8. A multi-core processor system comprising:
a plurality of central processing units (CPUs) including a first central processing unit (CPU) and a second CPU;
a scheduler corresponding to the first CPU;
a memory including a first storage area and a second storage area, the memory being connected via a bus to the CPUs; and
an address converter disposed between at least one CPU among the CPUs and the memory, wherein:
the address converter is configured to convert an address for accessing the first storage area managed by the first CPU, into an address for accessing the second storage area managed by the second CPU;
the address converter is further configured to convert the address for accessing the first storage area when a flag is on, the flag being configured to be set based on a type of a second thread that is generated based on a first thread executed by the first CPU and being configured to be set to on when the second thread is a blocking thread; and
a second thread context area is generated in the first storage area when it is determined that the second thread does not operate exclusively from the first thread.
9. The multi-core processor system according to claim 8 , wherein the address converter is further configured to convert the address for accessing the first storage area, based on an offset between an address of the first storage area and an address for accessing the first storage area by a second thread that is generated based on a first thread executed by the first CPU.
10. The multi-core processor system according to claim 8 , wherein the address converter is further configured to convert, responsive to access of the second storage area, an address of the second storage area into an address of the first storage area, based on an offset for the first storage area and a predetermined value.
11. The scheduling method according to claim 1 , wherein copying a first storage area accessed by the first thread onto a second storage area comprises copying data stored in the first storage area accessed by the first thread into the second storage area.
12. The scheduling method according to claim 1 , wherein the second thread comprises a blocking child thread of the first thread.
13. The scheduling method according to claim 12 , wherein execution of the first thread is suspended while the blocking child thread is being executed.