IP Library › Granted Patent US 9,293,550
Granted Patent B2
US 9,293,550 · App. 13/940,095 · Granted Mar 22, 2016

Semiconductor device and manufacturing method thereof

Inventor: Mieno Fumitake (Shanghai, CN)
Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
H01L29/4236H01L21/28088H01L21/823807H01L21/823842H01L29/401H01L29/4966H01L29/78H01L29/7845H01L29/66795H01L29/785
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Quick Facts
Patent No.
US 9,293,550
App. No.
13/940,095
Granted
Mar 22, 2016
Kind
B2
Abstract

The present invention discloses a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes a gate insulating layer formed on an inner wall of a substrate recess, a work function material layer formed on the gate insulating layer so as to apply a tensile stress or a compressive stress to a channel of a MOS field-effect transistor, and a gate metal formed on the work function material layer. The method for manufacturing the semiconductor device includes forming a work function material layer on a gate insulating layer so as to apply a tensile stress or a compressive stress to a channel of a MOS field-effect transistor, wherein the gate insulating layer is formed on an inner wall of a substrate recess, and depositing a gate metal on the work function material layer.

Claims (53)

1. A semiconductor device, comprising:

a gate insulating layer selectively formed on an inner wall of a silicon substrate recess;

a work function material layer directly formed on the gate insulating layer so as to apply a tensile stress or a compressive stress to a channel of a MOS field-effect transistor;

a gate metal formed on the work function material layer; and

a barrier layer formed between the work function material layer and the gate metal.

2. The semiconductor device according to claim 1 further comprising a gate structure of an nMOS field-effect transistor, and the work function material layer comprises a first work function material layer for applying a tensile stress to a channel of the nMOS field-effect transistor.

3. The semiconductor device according to claim 1 further comprising a gate structure of a pMOS field-effect transistor, and the work function material layer comprises a second work function material layer for applying a compressive stress to a channel of the pMOS field-effect transistor.

4. The semiconductor device according to claim 1 , further comprising:

a second metal layer formed on a surface common to the work function material layer, the barrier layer, and the gate metal.

5. The semiconductor device according to claim 1 , wherein the gate metal is formed so as to apply a tensile stress to the channel.

6. The semiconductor device according to claim 1 , further comprising:

a protection layer formed between the gate insulating layer and the work function material layer so as to protect the gate insulating layer.

7. A semiconductor device having a gate structure of an nMOS field-effect transistor, the semiconductor device comprising:

a gate insulating layer selectively formed on an inner wall of a silicon substrate recess;

a work function material layer directly formed on the gate insulating layer; and

a gate metal formed on the work function material layer so as to apply a tensile stress to a channel of the nMOS field-effect transistor; and

a barrier layer formed between the work function material layer and the gate metal.

8. The semiconductor device according to claim 7 , further comprising:

a second metal layer formed on a surface common to the work function material layer, the barrier layer, and the gate metal.

9. The semiconductor device according to claim 7 , wherein the work function material layer is formed so as to apply a tensile stress to the channel, and the work function material layer includes TiAlN, a metal carbide, or a metal oxycarbide.

10. The semiconductor device according to claim 7 , further comprising:

a protection layer formed between the gate insulating layer and the work function material layer so as to protect the gate insulating layer.

11. A method for manufacturing a semiconductor device, comprising:

selectively forming a gate insulating layer on an inner wall of a silicon substrate recess of a MOS field-effect transistor;

forming a work function material layer directly on the gate insulating layer so as to apply a tensile stress or a compressive stress to a channel of the MOS field-effect transistor;

depositing a gate metal on the work function material layer, and

forming a barrier layer between the work function material layer and the gate metal.

12. The method according to claim 11 , wherein the semiconductor device includes a gate structure of an nMOS field-effect transistor, and forming the work function material layer so as to apply a tensile stress to a channel of the nMOS field-effect transistor.

13. The method according to claim 11 , wherein the semiconductor device includes a gate structure of a pMOS field-effect transistor, and forming the work function material layer so as to apply a compressive stress to a channel of the pMOS field-effect transistor.

14. The method according to claim 11 , wherein the semiconductor device includes a gate structure of a CMOS field-effect transistor, and the substrate recess includes a first recess for a pMOS field-effect transistor and a second recess for an nMOS field-effect transistor; and

forming the work function material layer on the gate insulating layer comprises:

forming a first work function material layer for the pMOS field-effect transistor on respective gate insulating layers of the first recess and the second recess, so as to apply a compressive stress to the channel;

etching off an upper portion of the first work function material layer in the first recess and the first work function material layer in the second recess; and

forming a second work function material layer for the nMOS field-effect transistor in the first recess and the second recess, so as to apply a tensile stress to the channel.

15. The method according to claim 11 , wherein forming the work function material layer on the gate insulating layer comprises:

depositing a first work function material on the gate insulating layer; and

performing ion implantation on the first work function material so as to increase the applied compressive stress.

16. The method according to claim 11 , further comprising forming the gate metal so as to apply a tensile stress to the channel.

17. The method according to claim 11 , further comprising:

removing a portion of the work function material layer, the barrier layer, and the gate metal;

forming a second metal layer on a surface common to the work function material layer, the barrier layer, and the gate metal, so as to reduce contact resistance; and

depositing an insulator on the gate insulating layer and the second metal layer.

18. The method according to claim 11 , wherein forming the work function material layer on the gate insulating layer comprises:

forming a protection layer on the gate insulating layer; and

forming the work function material layer on the protection layer.

19. A method for manufacturing a semiconductor device having a gate structure of an nMOS field-effect transistor, the method comprising:

selectively forming a gate insulating layer on an inner wall of a silicon substrate recess of the nMOS field-effect transistor;

forming a work function material layer directly on the gate insulating layer; and

depositing a gate metal on the work function material layer so as to apply a tensile stress to a channel of the nMOS field-effect transistor, and

forming a barrier layer between the work function material layer and the gate metal.

20. The method according to claim 19 , wherein forming the work function material layer on the gate insulating layer comprises:

forming a protection layer on the gate insulating layer; and

forming the work function material layer on the protection layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 11, 2013
From: FUMITAKE, MIENO
To: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORATION (SHANGHAI)
Reel/Frame 030782/0196 →
Priority Claims (1)
CN 2012 1 0398918 · Oct 19, 2012 · national
Continuity (1)
Related Publication 20140110778A1 · Apr 24, 2014