Semiconductor device
A semiconductor device includes first and second well regions having a first conductivity type, and a third well region between the first and second well regions having a second conductivity type different from the first conductivity type. A first active region is in the first well region. A second active region is in the second well region. A third active region is in the third well region. The third active region is closer to the second active region than to the first active region. A fourth active region is in the third well region. The fourth active region is closer to the first active region than to the second active region. A first conductive pattern is across the first and third active regions. A second conductive pattern is across the second and fourth active regions and parallel to the first conductive pattern.
1. A semiconductor device comprising:
a semiconductor substrate including first and second well regions of a first conductivity type, and a third well region of a second conductivity type different from the first conductivity type, the third well region between the first and second well regions;
a first active region in the first well region;
a second active region in the second well region;
a third active region in the third well region, the third active region closer to the second active region than to the first active region;
a fourth active region in the third well region, the fourth active region closer to the first active region than to the second active region;
a first conductive pattern across only the first and third active regions;
a second conductive pattern across the second and fourth active regions;
a third conductive pattern across the first active region; and
a fourth conductive pattern across the second active region,
wherein the second and third conductive patterns have end portions that face each other and the facing end portions of the second and third conductive patterns are between the first and third active regions, and
wherein the first and fourth conductive patterns have end portions that face each other and the facing end portions of the first and fourth conductive patterns are between the second and fourth active regions.
2. The device of claim 1 , wherein one end portion of the third active region is between the second and fourth active regions, and one end portion of the fourth active region is between the first and third active regions.
3. The device of claim 1 , wherein
each of the first and second active regions includes a first portion having a first width, and a second portion having a second width smaller than the first width,
the first portion of the first active region faces the second portion of the second active region, and
the second portion of the first active region faces the first portion of the second active region.
4. The device of claim 3 , wherein
a portion of the third active region facing the second portion of the second active region is larger than a portion of the third active region facing the first portion of the second active region, and
a portion of the fourth active region facing the second portion of the first active region is larger than a portion of the fourth active region facing the first portion of the first active region.
5. The device of claim 3 , wherein
the first conductive pattern has a bar shape across the first portion of the first active region and the third active region, and
the second conductive pattern has a bar shape across the first portion of the second active region and the fourth active region.
6. The device of claim 1 , further comprising:
a lower gate dielectric material, a middle gate dielectric material, and an upper gate dielectric material sequentially stacked on the semiconductor substrate, the lower gate dielectric material, the middle gate dielectric material and the upper gate dielectric material between the first conductive pattern and the third active region,
wherein the upper gate dielectric material overlaps both the third active region and the first active region, and
an end portion of the middle gate dielectric material is between the first and third active regions.
7. The device of claim 1 , wherein the second conductive pattern crosses only the second and fourth active regions.
8. The device of claim 1 , wherein
each of the first and second active regions includes a first end portion having a first width, and a second end portion having a second width smaller than the first width;
the first end portion of the first active region faces inward towards the second end portion of the second active region such that a sidewall of the first end portion is closer to the fourth active region than a sidewall of the second end portion; and
the first end portion of the second active region faces inward towards the second end portion of the first active region such that a sidewall of the first end portion is closer to the third active region than a sidewall of the second end portion.