Non-volatile semiconductor storage device
View Patent ↗For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage.
1. A non-volatile semiconductor storage device comprising:
a memory cell array including an electrically rewritable non-volatile memory cell arranged therein; and
a control unit configured to perform controlling of repeating an erase operation to apply an erase pulse voltage to the memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed,
the control unit configured to, when controlling of repeating the erase operation, the erase verify operation and the step-up operation is performed, generate a first erase pulse voltage in a first one of the erase operations as an initial pulse voltage, and thereafter generate a second erase pulse voltage in a second one of the erase operations subsequent to the first one of the erase operations,
the control unit configured to control the erase pulse voltage such that:
the second erase pulse voltage has a voltage value at a saturation state larger than that of the first erase pulse voltage, and
the first erase pulse voltage is longer than the second erase pulse voltage with respect to a width of a blunted wave-shape portion thereof, the blunted wave-shape portion being continuous to the voltage value at the saturation state, and
the control unit configured to control a voltage of the first erase pulse voltage such that a voltage wave shape of the first erase pulse voltage when a vertical axis thereof denotes a voltage and a lateral axis denotes time has a gradient that a gradient at a first point of time is not larger than a gradient at a second point of time before the first point of time through the width of the blunted wave-shape portion, the blunted wave-shape portion being continuous to the voltage value at the saturation state of the first erase pulse voltage.
2. The non-volatile semiconductor storage device according to claim 1 , wherein
the control unit is configured to, when controlling of repeating the erase operation, the erase verify operation and the step-up operation is performed, further generate a third erase pulse voltage in a third one of the erase operations subsequent to the second one of the erase operations, and
the control unit is configured to control the erase pulse voltage such that:
in the first one of the erase operations, the first erase pulse voltage reaches a first saturation value,
in the second one of the erase operations, the second erase pulse voltage reaches a second saturation value,
in the third one of the erase operations, the third erase pulse voltage reaches a third saturation value,
the erase pulse voltage is increased by the certain step-up voltage from the first saturation value to the second saturation value, and from the second saturation value to the third saturation value, a difference between the first saturation value and the second saturation value and a difference between the second saturation value and the third saturation value being equal to each other, and
the width of the blunted wave-shape portion that is continuous to the first saturation value in the first erase pulse voltage is set such that the first erase pulse voltage is longer than the second erase pulse voltage with respect to the width of the blunted wave-shape portion.
3. The non-volatile semiconductor storage device according to claim 1 , wherein
the control unit controls a voltage of the first erase pulse voltage such that the blunted wave-shape portion thereof rises from 0 V to continue to the voltage value at the saturation state thereof.
4. The non-volatile semiconductor storage device according to claim 1 , wherein
the control unit controls a voltage of the first erase pulse voltage such that the voltage is progressively increased following a rise curve until the voltage reaches the saturation state.
5. The non-volatile semiconductor storage device according to claim 1 , wherein
a relation of Wp/3≦t is satisfied, wherein Wp is a pulse width of the first erase pulse voltage, and t is the width of the blunted wave-shape portion of the first erase pulse voltage.
6. A non-volatile semiconductor storage device comprising:
a memory cell array including an electrically rewritable non-volatile memory cell arranged therein; and
a control unit configured to perform controlling of repeating an erase operation to apply an erase pulse voltage to the memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed,
the control unit being configured to, when controlling of repeating the erase operation, the erase verify operation and the step-up operation is performed, generate a first erase pulse voltage in a first one of the erase operations as an initial pulse voltage, and thereafter generate a second erase pulse voltage in a second one of the erase operations subsequent to the first one of the erase operations,
the control unit being configured to control the erase pulse voltage such that:
the second erase pulse voltage has a voltage value at a saturation state larger than that of the first erase pulse voltage, and
the first erase pulse voltage is longer than the second erase pulse voltage with respect to a width of a blunted wave-shape portion thereof, the blunted wave-shape portion being a single rise curve and continuous to the voltage value at the saturation state, and
the control unit being configured to control a voltage of the first erase pulse voltage such that the blunted wave-shape portion including the single rise curve is followed by a substantially flat area having the voltage value at the saturation state of the first erase pulse voltage.
7. The non-volatile semiconductor storage device according to claim 6 , wherein
the control unit is configured to, when controlling of repeating the erase operation, the erase verify operation and the step-up operation is performed, further generate a third erase pulse voltage in a third one of the erase operations subsequent to the second one of the erase operations, and
the control unit is configured to control the erase pulse voltage such that:
in the first one of the erase operations, the first erase pulse voltage reaches a first saturation value,
in the second one of the erase operations, the second erase pulse voltage reaches a second saturation value,
in the third one of the erase operations, the third erase pulse voltage reaches a third saturation value,
the erase pulse voltage is increased by the certain step-up voltage from the first saturation value to the second saturation value, and from the second saturation value to the third saturation value, a difference between the first saturation value and the second saturation value and a difference between the second saturation value and the third saturation value being equal to each other, and
the width of the blunted wave-shape portion that is continuous to the first saturation value in the first erase pulse voltage is set such that the first erase pulse voltage is longer than the second erase pulse voltage with respect to the width of the blunted wave-shape portion.
8. The non-volatile semiconductor storage device according to claim 6 , wherein
the control unit controls a voltage of the first erase pulse voltage such that the blunted wave-shape portion thereof rises from 0 V to continue to the voltage value at the saturation state thereof.
9. The non-volatile semiconductor storage device according to claim 6 , wherein
a relation of Wp/3≦t is satisfied, wherein Wp is a pulse width of the first erase pulse voltage, and t is the width of the blunted wave-shape portion of the first erase pulse voltage.
10. A non-volatile semiconductor storage device comprising:
a memory cell array including an electrically rewritable non-volatile memory cell arranged therein;
a control unit configured to perform controlling of repeating an erase operation to apply an erase pulse voltage to the memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed;
a voltage generation circuit including N (N≧2) boost circuits, each configured to generate a boosted voltage based on a power supply voltage; and
a pulse generation circuit configured to generate the erase pulse voltage using the boosted voltage,
the control unit configured to, when controlling of repeating the erase operation, the erase verify operation and the step-up operation is performed, generate a first erase pulse voltage in a first one of the erase operations as an initial pulse voltage, and thereafter generate a second erase pulse voltage in a second one of the erase operations subsequent to the first one of the erase operations,
the control unit configured to control the erase pulse voltage such that:
the second erase pulse voltage has a voltage value at a saturation state larger than that of the first erase pulse voltage, and
the first erase pulse voltage is longer than the second erase pulse voltage with respect to a width of a blunted wave-shape portion thereof, the blunted wave-shape portion being continuous to the voltage value at the saturation state, and
the control unit configured to drive M (M<N) of the boost circuits in generating the first erase pulse voltage, and drive L (L>M) of the boost circuits in generating the second erase pulse voltage.
11. The non-volatile semiconductor storage device according to claim 10 , wherein
the control unit is configured to, when controlling of repeating the erase operation, the erase verify operation and the step-up operation is performed, further generate a third erase pulse voltage in a third one of the erase operations subsequent to the second one of the erase operations, and
the control unit is configured to control the erase pulse voltage such that:
in the first one of the erase operations, the first erase pulse voltage reaches a first saturation value,
in the second one of the erase operations, the second erase pulse voltage reaches a second saturation value,
in the third one of the erase operations, the third erase pulse voltage reaches a third saturation value,
the erase pulse voltage is increased by the certain step-up voltage from the first saturation value to the second saturation value, and from the second saturation value to the third saturation value, a difference between the first saturation value and the second saturation value and a difference between the second saturation value and the third saturation value being equal to each other, and
the width of the blunted wave-shape portion that is continuous to the first saturation value in the first erase pulse voltage is set such that the first erase pulse voltage is longer than the second erase pulse voltage with respect to the width of the blunted wave-shape portion.
12. The non-volatile semiconductor storage device according to claim 10 , wherein
the control unit controls a voltage of the first erase pulse voltage such that the blunted wave-shape portion thereof rises from 0 V to continue to the voltage value at the saturation state thereof.
13. The non-volatile semiconductor storage device according to claim 10 , wherein
the control unit controls a voltage of the first erase pulse voltage such that the voltage is progressively increased following a rise curve until the voltage reaches the saturation state.
14. The non-volatile semiconductor storage device according to claim 10 , wherein
a relation of Wp/3≦t is satisfied, wherein Wp is a pulse width of the first erase pulse voltage, and t is the width of the blunted wave-shape portion of the first erase pulse voltage.