IP Library Granted Patent US 10,176,121
Granted Patent B2
US 10,176,121 · App. 13/942,096 · Granted Jan 8, 2019

Apparatus and method for memory address encryption

Inventor: Berndt Gammel (Markt Schwaben, DE)
Assignee: Infineon Technologies AG
G06F12/1408G06F12/10G06F2212/1024G06F2212/1028Y02D10/13
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Quick Facts
Patent No.
US 10,176,121
App. No.
13/942,096
Granted
Jan 8, 2019
Kind
B2
Abstract

An apparatus for encrypting an input memory address to obtain an encrypted memory address is provided. The apparatus comprises an input interface for receiving the input memory address being an address of a memory. Moreover, the apparatus comprises an encryption module for encrypting the input memory address depending on a cryptographic key to obtain the encrypted memory address. The encryption module is configured to encrypt the input memory address by applying a map mapping the input memory address to the encrypted memory address, wherein the encryption module is configured to apply the map by conducting a multiplication and a modulo operation using the cryptographic key and a divisor of the modulo operation, such that the map is bijective.

Claims (44)

1. An apparatus for accessing a memory using encrypted memory addresses, comprising:

an input interface configured to receive an input memory address being a logical address used by a microprocessor for storing and retrieving data, and

an encryption module configured to encrypt the input memory address depending on a cryptographic key to obtain an encrypted memory address and to apply the encrypted memory address to the memory as a physical memory address, for retrieval or storage of data at the physical memory address,

wherein the encryption module is configured to encrypt the input memory address by applying a map mapping the input memory address to the encrypted memory address, wherein the encryption module is configured to apply the map by conducting a multiplication and a modulo operation using the cryptographic key and a divisor of the modulo operation, such that the map is bijective,

wherein the apparatus is implemented using a hardware apparatus or using a computer or using a combination of a hardware apparatus and a computer.

2. An apparatus according to claim 1 , wherein the input memory address indicates a first polynomial, wherein the encrypted memory address indicates a second polynomial, wherein the cryptographic key indicates a third polynomial, and wherein the divisor indicates a fourth polynomial being an irreducible polynomial.

3. An apparatus according to claim 1 ,

wherein the encryption module is configured to apply the map by employing the formula:

a′=a k (mod p ),

wherein a indicates the input memory address,

wherein a′ indicates the encrypted memory address,

wherein k indicates the encryption key, and

wherein p indicates the divisor.

4. An apparatus according to claim 3 , wherein the apparatus is configurable to select an identity key as the encryption key k, such that a k (mod p)=a mod p.

5. An apparatus according to claim 3 , wherein the apparatus is configurable to select a zero key as the encryption key k, such that a k (mod p)=0.

6. An apparatus according to claim 1 ,

wherein the encryption module is configured to apply the map by employing the formula

a′=a k (mod p ) + b,

wherein a indicates the input memory address,

wherein a′ indicates the encrypted memory address,

wherein k indicates the encryption key,

wherein p indicates the divisor, and

wherein b indicates an auxiliary key.

7. An apparatus according to claim 6 , wherein the apparatus is configurable to select an identity key as the encryption key k, such that

a k (mod p ) +b=a mod p+b.

8. An apparatus according to claim 6 , wherein the apparatus is configurable to select a zero key as the encryption key k, such that a k (mod p)+b=b.

9. An apparatus comprising:

a memory

a microprocessor configured to process data being stored at memory addresses in the memory, and

an address encryption unit configured to encrypt an input memory address of the memory to obtain an encrypted memory address, wherein the address encryption unit comprises:

an input interface configured to receive the input memory address being a logical address used by the microprocessor for storing and retrieving data, and

an encryption module configured to encrypt the input memory address depending on a cryptographic key to obtain the encrypted memory address and to apply the encrypted memory address to the memory as a physical memory address, for retrieval and storage of data at the physical memory address,

wherein the encryption module is configured to encrypt the input memory address by applying a map mapping the input memory address to the encrypted memory address, wherein the encryption module is configured to apply the map by conducting a multiplication and a modulo operation using the cryptographic key and a divisor of the modulo operation, such that the map is bijective,

wherein the apparatus is implemented using a hardware apparatus or using a computer or using a combination of a hardware apparatus and a computer.

10. A method for accessing a memory using encrypted memory addresses, comprising:

receiving an input memory address being a logical address used by a microprocessor for storing and retrieving data, and

encrypting the input memory address depending on a cryptographic key to obtain an encrypted memory address and to apply the encrypted memory address to the memory as a physical memory address, for retrieval or storage of data at the physical memory address,

wherein encrypting the input memory address comprises applying a map mapping the input memory address to the encrypted memory address by conducting a multiplication and a modulo operation using the cryptographic key and a divisor of the modulo operation, such that the map is bijective,

wherein the method is performed using a hardware apparatus or using a computer or using a combination of a hardware apparatus and a computer.

11. A method according to claim 10 , wherein the input memory address indicates a first polynomial, wherein the encrypted memory address indicates a second polynomial, wherein the cryptographic key indicates a third polynomial, and wherein the divisor indicates a fourth polynomial being an irreducible polynomial.

12. A non-transitory digital storage medium having stored thereon a computer program for performing a method for accessing a memory using encrypted memory addresses, comprising:

receiving an input memory address being a logical address used by a microprocessor for storing and retrieving data; and

encrypting the input memory address depending on a cryptographic key to obtain an encrypted memory address and to apply the encrypted memory address to the memory as a physical memory address, for retrieval or storage of data at the physical memory address,

wherein encrypting the input memory address comprises applying a map mapping the input memory address to the encrypted memory address by conducting a multiplication and a modulo operation using the cryptographic key and a divisor of the modulo operation, such that the map is bijective.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 4, 2013
From: GAMMEL, BERNDT
To: INFINEON TECHNOLOGIES AG
Reel/Frame 031351/0561 →
Continuity (1)
Related Publication 20150019878A1 · Jan 15, 2015
Cited By (1)
US 12,189,833