Memory device
A memory device according to an embodiment, includes a substrate, two or more resistance change memory cells stacked on the substrate, two or more transistors stacked on the substrate, and two or more wirings stacked on the substrate. One of the memory cells and one of the transistors are connected to each other via one of the wirings.
1. A memory device comprising:
word line wiring layers, each of the word line wiring layers including a plurality of first word lines extending in a first direction and a plurality of second word lines extending in the first direction;
bit line wiring layers, each of the bit line wiring layers including a plurality of first bit lines extending in a second direction crossing the first direction and a plurality of second bit lines extending in the second direction;
a memory cell connected between each of the first word lines and each of the first bit lines;
a first semiconductor layer provided across each of the first word lines and each of the second word lines;
a first gate provided on the first semiconductor layer;
a first insulating layer provided between the first semiconductor layer and the first gate;
a second semiconductor layer provided across each of the first bit lines and each of the second bit lines;
a second gate provided on the second semiconductor layer; and
a second insulating layer provided between the second semiconductor layer and the second gate,
first sets each of which include the first semiconductor layer, the first gate and the first insulating layer, each of the first sets being disposed with each of the word line wiring layers,
second sets each of which include the second semiconductor layer, the second gate and the second insulating layer, each of the second sets being disposed with each of the bit line wiring layers,
each of the word line wiring layers and each of the bit line wiring layers being alternately stacked,
the first sets being stacked in a stacking direction of the word line wiring layers and the bit line wiring layers, and
the second sets being stacked in the stacking direction.
2. The device according to claim 1 , wherein
material of the first gate is same as material of the first and second bit lines, and
material of the second gate is same as material of the first and second word lines.
3. The device according to claim 1 , wherein
the memory cell includes:
a silicon layer; and
a silicon oxide layer,
the first semiconductor layer and the second semiconductor layer are silicon layers, and
the first insulating layer and the second insulating layer are silicon oxide layers.
4. The device according to claim 1 , wherein gate length direction of the first gate is the first direction, and gate length direction of the second gate is the second direction.
5. The device according to claim 1 , wherein gate width direction of the first gate is the first direction, and gate width direction of the second gate is the second direction.
6. The device according to claim 1 , wherein in the first and second word lines, width of end portions is wider than width of a portion in contact with the memory cell.
7. The device according to claim 1 , wherein in the first and second word lines, width of end portions is nearly equal to width of a portion in contact with the memory cell.
8. The device according to claim 1 , wherein the first gate, the first insulating layer, and the first semiconductor layer constitute a first transistor, and the first transistors are arranged like a matrix.
9. The device according to claim 1 , wherein the first gate, the first insulating layer, and the first semiconductor layer constitute a first transistor, and a first transistor region including the first transistor is placed so as to sandwich a memory cell array including the memory cell.
10. The device according to claim 1 , wherein the first gate, the first insulating layer, and the first semiconductor layer constitute a first transistor, and the first transistors are arranged in a line in the second direction.
11. A memory device comprising:
word line wiring layers, each of the word line wiring layers including a plurality of first word lines extending in a first direction and a plurality of second word lines extending in the first direction;
bit line wiring layers, each of the bit line wiring layers including a plurality of first bit lines extending in a second direction crossing the first direction and a plurality of second bit lines extending in the second direction;
a memory cell connected between each of the first word lines and each of the first bit lines, the memory cell includes:
a first silicon oxide layer;
a first silicon layer; and
a second silicon oxide layer;
a second silicon layer provided across each of the first word lines and each of the second word lines;
a first gate provided on the second silicon layer;
a third silicon oxide layer provided between the second silicon layer and the first gate;
a third silicon layer provided across each of the first bit lines and each of the second bit lines;
a second gate provided on the third silicon layer; and
a fourth silicon oxide layer provided between the third silicon layer and the second gate,
first sets each of which include the second silicon layer, the first gate and the third silicon oxide layer, each of first sets being disposed with each of the word line wiring layers,
second sets each of which include the third silicon layer, the second gate and the fourth silicon oxide layer, each of second sets being disposed with each of the bit line wiring layers,
each of the word line wiring layers and each of the bit line wiring layers being alternately stacked,
the first sets being stacked in a stacking direction of the word line wiring layers and the bit line wiring layers, and
the second sets being stacked in the stacking direction.