Nonvolatile semiconductor memory device

1. A nonvolatile semiconductor memory device comprising:

a memory cell array including memory cell transistors configured to store information in accordance with n (n is an integer larger than 2) threshold voltage levels; and

a control circuit configured to control the memory cell array,

wherein in a write operation, the control circuit shifts a threshold voltage level of a write target memory cell transistor to a base threshold level of the n threshold levels, except for a threshold level having a highest voltage and a threshold level having a lowest voltage, and then shifts the threshold level of the write target memory cell transistor from the base threshold level to one of the n threshold levels.

2. The nonvolatile semiconductor memory device of claim 1 , wherein the base threshold level is a threshold level which minimizes an average threshold voltage shift amount when the threshold voltage level of the write target memory cell transistor is shifted from the base threshold level to one of the n threshold levels.

3. The nonvolatile semiconductor memory device of claim 1 , wherein

the memory cell transistors are n-type channel transistors, and store information in accordance with four threshold voltage levels, and

the base threshold level is a second threshold level from the threshold level having a lowest voltage of the four threshold levels.

4. The nonvolatile semiconductor memory device of claim 3 , wherein a channel material of the memory cell transistors contains Si.

5. The nonvolatile semiconductor memory device of claim 1 , wherein

the memory cell transistors are n-type channel transistors, and store information in accordance with eight threshold voltage levels, and

the base threshold level is a fourth threshold level from the threshold level having a lowest voltage of the eight threshold levels.

6. The nonvolatile semiconductor memory device of claim 5 , wherein a channel material of the memory cell transistors contains Si.

7. The nonvolatile semiconductor memory device of claim 1 , wherein

the memory cell transistors are p-type channel transistors, and store information in accordance with four threshold voltage levels, and

the base threshold level is a third threshold level from the threshold level having a highest (most positive) voltage of the four threshold levels.

8. The nonvolatile semiconductor memory device of claim 7 , wherein a channel material of the memory cell transistors contains Ge.

9. The nonvolatile semiconductor memory device of claim 1 , wherein

the memory cell transistors are p-type channel transistors, and store information in accordance with eight threshold voltage levels, and

the base threshold level is a fifth threshold level from the threshold level having a highest (most positive) voltage of the eight threshold levels.

10. The nonvolatile semiconductor memory device of claim 9 , wherein a channel material of the memory cell transistors contains Ge.

11. The nonvolatile semiconductor memory device of claim 1 , wherein the memory cell transistors comprise:

an inter-electrode insulating layers and word lines alternately stacked above a semiconductor substrate;

a block insulating layer formed on an inner surface of a memory hole extending through the inter-electrode insulating layers and the word lines;

a charge storage layer formed on the block insulating layer;

a tunnel insulating layer formed on the charge storage layer; and

a semiconductor layer formed on the tunnel insulating layer.

12. The nonvolatile semiconductor memory device of claim 1 , wherein the memory cell transistors comprise:

a backgate formed above a semiconductor substrate, and inter-electrode insulating layers and word lines alternately stacked above the backgate;

a block insulating layer formed on inner surfaces of a pair of through holes formed in the inter-electrode insulating layers and the word lines, and extending in a stacking direction, and on an inner surface of a connecting hole which is formed in the backgate and connects lower ends of the pair of through holes;

a charge storage layer formed on the block insulating layer;

a tunnel insulating layer formed on the charge storage layer; and

a semiconductor layer formed on the tunnel insulating layer.

13. A nonvolatile semiconductor memory device comprising:

a memory cell array containing a memory string including memory cell transistors configured to store information in accordance with n (n is an integer larger than 2) threshold voltage levels and configured to have current paths connected in series;

a drain-side selection transistor including a current path having one end connected to one end of a current path of the memory string, and the other end connected to a bit line;

a source-side selection transistor including a current path having one end connected to the other end of the current path of the memory string, and the other end connected to a source line; and

a control circuit configured to control the memory cell array, the drain-side selection transistor, and the source-side selection transistor,

wherein in a write operation, the control circuit shifts a threshold voltage level of a write target memory cell transistor to a base threshold level of the n threshold levels, except for a threshold level having a highest voltage and a threshold level having a lowest voltage, and then shifts the threshold voltage level of the write target memory cell transistor from the base threshold level to one of the n threshold levels, and

when shifting the threshold voltage level of the write target memory cell transistor from the base threshold level to a threshold level lower than the base threshold level or to a threshold level higher than the base threshold level, the control circuit supplies a GIDL (Gate-Induced Drain Leakage) current generated by a potential difference between the bit line and a gate of the drain-side selection transistor to the write target memory cell transistor.

14. The nonvolatile semiconductor memory device of claim 13 , wherein the base threshold level is a threshold voltage level which minimizes an average threshold voltage shift amount when the threshold level of the write target memory cell transistor is shifted from the base threshold level to one of the n threshold levels.

15. The nonvolatile semiconductor memory device of claim 13 , wherein

the memory cell transistors are n-type channel transistors, and store information in accordance with four threshold voltage levels,

the base threshold level is a second threshold level from the threshold level having a lowest voltage of the four threshold levels, and

when shifting the threshold voltage level of the write target memory cell transistor from the base threshold level to a threshold level lower than the base threshold level, the control circuit supplies the GIDL current to the write target memory cell transistor.

16. The nonvolatile semiconductor memory device of claim 15 , wherein a channel material of the memory cell transistors contains Si.

17. The nonvolatile semiconductor memory device of claim 13 , wherein

the memory cell transistors are p-type channel transistors, and store information in accordance with eight threshold levels,

the base threshold level is a third threshold level from the threshold level having a highest (most positive) voltage of the four threshold levels, and

when shifting the threshold voltage level of the write target memory cell transistor from the base threshold level to a threshold level higher (more positive) than the base threshold level, the control circuit supplies the GIDL current to the write target memory cell transistor.

18. The nonvolatile semiconductor memory device of claim 17 , wherein a channel material of the memory cell transistors contains Ge.

19. The nonvolatile semiconductor memory device of claim 13 , wherein the memory string comprises:

an inter-electrode insulating layers and word lines alternately stacked above a semiconductor substrate;

a block insulating layer formed on an inner surface of a memory hole extending through the plurality of inter-electrode insulating layers and the plurality of word lines;

a charge storage layer formed on the block insulating layer;

a tunnel insulating layer formed on the charge storage layer; and

a semiconductor layer formed on the tunnel insulating layer.

20. The nonvolatile semiconductor memory device of claim 13 , wherein the memory string comprises:

a backgate formed above a semiconductor substrate, and an inter-electrode insulating layers and word lines alternately stacked above the backgate;

a block insulating layer formed on inner surfaces of a pair of through holes formed in the inter-electrode insulating layers and the word lines, and extending in a stacking direction, and on an inner surface of a connecting hole which is formed in the backgate and connects lower ends of the pair of through holes;

a charge storage layer formed on the block insulating layer;

a tunnel insulating layer formed on the charge storage layer; and

a semiconductor layer formed on the tunnel insulating layer.