Multilayer interconnect structure and method for integrated circuits
View Patent ↗A multilayer interconnect structure is formed by, providing a substrate ( 40 ) having thereon a first dielectric ( 50, 27 ) for supporting a multi-layer interconnection ( 39 ) having lower conductor M N ( 22, 23 ), upper conductor M N+1 ( 34, 35 ), dielectric interlayer (DIL) ( 68 ) and interconnecting via conductor V N+1/N ( 36, 36 ′). The lower conductor M N ( 22, 23 ) has a first upper surface ( 61 ) located in a recess below a second upper surface ( 56 ) of the first dielectric ( 50, 27 ). The DIL ( 68 ) is formed above the first ( 61 ) and second ( 56 ) surfaces. A cavity ( 1263 ) is etched through the DIL ( 68 ) from a desired location ( 122 ) of the upper conductor M N+1 ( 34 ), exposing the first surface ( 61 ). The cavity ( 1263 ) is filled with a further electrical conductor ( 80 ) to form the upper conductor M N+1 ( 34 ) and the connecting via conductor V N+1/N ( 36, 36 ′) making electrical contact with the first upper surface ( 61 ). A critical dimension ( 32, 37 ) between others ( 23 ) of lower conductors M N ( 22, 23 ) and the via conductor V N+1/N ( 36, 36 ′) is lengthened. Leakage current and electro-migration there-between are reduced.
1. An integrated circuit (IC) having therein one or more multilayer interconnections, comprising:
one or more first level conductors M N , one or more second level conductors M N+1 and at least one via conductor V N±1/N coupling at least one second level conductor M N+1 to at least one first level conductor M N ; and
wherein an upper portion of the at least one via conductor V N+1/N is self-aligned with the at least one second level conductor M N+1 and a lower portion of the at least one via conductor V N+1/N is self-aligned with the at least one first level conductor M N .
2. The integrated circuit (IC) of claim 1 , further comprising a lateral step in the at least one via conductor V N+1/N where the upper portion and lower portion meet.
3. The integrated circuit (IC) of claim 2 , wherein the first level conductor M N comprises at least first and second conductors M N separated by a first lateral distance and wherein the first of the at least two conductors M N connects to the at least one via conductor V N+1/N and the lateral step in the at least one via conductor V N+1/N is separated from the second of the at least two conductors M N by a distance larger than if the second of the at least two conductors M N extended to the same level as the lateral step.
4. The integrated circuit (IC) of claim 2 , wherein the lateral step occurs at a change in lateral width of the at least one via conductor V N+1/N from a first value in the upper portion to a second different value in the lower portion.
5. The integrated circuit (IC) of claim 1 , wherein the upper portion of the at least one via conductor V N+1/N has a first lateral width corresponding substantially to a lateral width of an overlying at least one second level conductor M N+1 and the lower portion of the at least one via conductor V N+1/N has a second lateral width corresponding substantially to a lateral width of an underlying at least one first level conductor M N+1 and the lateral-width transition occurs at a level above a level of another of the first level conductors M N .
6. The integrated circuit (IC) of claim 1 , wherein the upper portion of the at least one via conductor V N+1/N of first lateral width and the lower portion of the at least one via conductor V N+1/N with a second lateral width are not symmetrically laterally disposed one with another.