Core circuit including dual mode TAP and scan test port
Connection circuitry couples scan test port (STP) circuitry to test access port (TAP) circuitry. The connection circuitry has inputs connected to scan circuitry control output leads from the TAP circuitry, a select input lead, and a clock input lead. The connection circuitry has outputs connected to a scan enable (SE) input lead, a capture select (CS) input lead, and the scan clock (CK) input lead of the STP circuitry. The connection circuitry includes a multiplexer having a control input connected with a clock select lead from the TAP circuitry, an input connected with a functional clock lead, an input connected with the clock input lead, an input connected with a Clock-DR lead from the TAP circuitry, an OFF lead, and an output connected with the scan clock input lead.
1. An integrated circuit comprising:
A. a test data in and serial data in lead;
B. a test mode select and capture scan lead;
C. a test clock and scan clock lead;
D. a test data out and serial data out lead;
E. a first core circuit including first dual mode test access port and scan test port circuitry having a test data and serial data input connected to the test data in and serial data in lead, having a test mode select and capture scan input connected to the test mode select and capture scan lead, having a test clock and scan clock input connected to the test clock and scan clock lead, and having a test data out and serial data out output coupled to the test data out and serial data out lead.
2. The integrated circuit of claim 1 including a second core circuit including second dual mode test access port and scan test port circuitry having a test data and serial data input connected to the test data out and serial data out output of the first dual mode test access port and scan test port circuitry, having a test mode select and capture scan input connected to the test mode select and capture scan lead, having a test clock and scan clock input connected to the test clock and scan clock lead, and having a test data out and serial data out output coupled to the test data out and serial data out lead.
3. The integrated circuit of claim 2 in which the first and second dual mode test access port and scan test port circuitry each include a test access port, a scan test port, and connection circuitry connecting the test access port to the scan test port.
4. The integrated circuit of claim 1 including:
A. a second core circuit including second dual mode test access port and scan test port circuitry having a test data and serial data input connected to the test data out and serial data out output of the first dual mode test access port and scan test port circuitry, having a test mode select and capture scan input connected to the test mode select and capture scan lead, having a test clock and scan clock input connected to the test clock and scan clock lead, and having a test data out and serial data out output coupled to the test data out and serial data out lead, and
B. a third core circuit including third dual mode test access port and scan test port circuitry having a test data and serial data input connected to the test data out and serial data out output of the second dual mode test access port and scan test port circuitry, having a test mode select and capture scan input connected to the test mode select and capture scan lead, having a test clock and scan clock input connected to the test clock and scan clock lead, and having a test data out and serial data out output connected to the test data out and serial data out lead.
5. The integrated circuit of claim 4 in which the first, second, and third dual mode test access port and scan test port circuitry each include a test access port, a scan test port, and connection circuitry connecting the test access port to the scan test port.
6. The integrated circuit of claim 1 in which the first dual mode test access port and scan test port circuitry includes a test access port, a scan test port, and connection circuitry connecting the test access port to the scan test port.