Circuit and system of using junction diode as program selector for one-time programmable devices
Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The OTP device has an OTP element coupled to a diode in a memory cell. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. By applying a high voltage to the P terminal of a diode and switching the N terminal of a diode to a low voltage for suitable duration of time, a current flows through an OTP element in series with the program selector may change the resistance state. The P+ active region of the diode can be isolated from the N+ active region in the N well by using dummy MOS gate, SBL, or STI/LOCOS isolations. If the resistive element is an interconnect fuse based on CMOS gate material, the resistive element can be coupled to the P+ active region by an abutted contact such that the element, active region, and metal are connected in a single rectangular contact.
1. A One-Time Programmable (OTP) memory, comprising:
a plurality of OTP cells, at least one of the cells comprising:
an OTP element coupled to a first supply voltage line;
a diode including at least a first active region and a second active region, where the first active region having a first type of dopant and a second active region having a second type of dopant, the first active region associated with a first terminal of the diode, the second active region associated with a second terminal of the diode, both the first and second active regions residing in a common well, the first active region coupled to the OTP element and the second active region coupled to a second supply voltage line,
wherein the first and second active regions being fabricated from sources or drains of CMOS devices, and the well is fabricated from wells in CMOS technologies, and
wherein the OTP element is configured to be programmable by applying voltages to the first and the second supply voltage lines to thereby change its logic state,
wherein the first and second active regions are separated by at least one of shallow trench isolation, a dummy CMOS gate, or a silicide block layer.
2. An OTP memory as recited in claim 1 , wherein the first or second active region of the diode has no more than two contacts.
3. An OTP memory as recited in claim 1 , wherein the first and second active regions are separated by at least two of shallow trench isolation, a dummy CMOS gate, or a silicide block layer.
4. An OTP memory as recited in claim 1 , wherein the first and second active regions are separated by shallow trench isolation.
5. An OTP memory as recited in claim 1 , wherein the first and second active regions are separated by a dummy CMOS gate.
6. An OTP memory as recited in claim 1 , wherein the first and second active regions are separated by a silicide block layer.
7. An OTP memory as recited in claim 1 , wherein the OTP element is a conductive contact or via.
8. An OTP memory as recited in claim 1 , wherein the OTP element is an anti-fuse constructed from a thin gate oxide between CMOS gate and body.
9. An OTP memory as recited in claim 1 , wherein the OTP element is an anti-fuse constructed from one or more contacts or vias with dielectrics in between.
10. An electronics system, comprising:
a processor; and
an One-Time Programmable (OTP) memory operatively connected to the processor, the OTP memory including a plurality of OTP cells, at least one of the cells comprising:
an OTP element coupled to a first supply voltage line;
a diode including at least a first active region and a second active region, where the first active region having a first type of dopant and the second region having a second type of dopant, the first active region associated with a first terminal of the diode, the second active region associated with a second terminal of the diode, both the first and second active regions residing in a common well, the first active region coupled to the OTP element, and the second active region coupled to a second supply voltage line,
wherein the first and second active regions being fabricated from sources or drains of CMOS devices, and the well is fabricated from wells in CMOS technologies, and
wherein the OTP element is configured to be programmable by applying voltages to the first and the second supply voltage lines to thereby change the resistance into a different logic state,
wherein the first and second active regions are separated by at least one of shallow trench isolation, a dummy CMOS gate, or a silicide block layer.
11. An electronics system as recited in claim 10 , wherein the first or second active region of the diode has no more than two contacts.
12. An electronics system as recited in claim 10 , wherein the first and second active regions are separated by at least two of shallow trench isolation, a dummy CMOS gate, or a silicide block layer.
13. An electronics system as recited in claim 10 , wherein the first and second active regions are separated by shallow trench isolation.
14. An electronics system as recited in claim 10 , wherein the first and second active regions are separated by a dummy CMOS gate.
15. An electronics system as recited in claim 10 , wherein the first and second active regions are separated by a silicide block layer.
16. An electronics system as recited in claim 10 , wherein the OTP element is a conductive contact or via.
17. An electronics system as recited in claim 10 , wherein the OTP element is an anti-fuse constructed from a thin gate oxide between CMOS gate and body.
18. An electronics system as recited in claim 10 , wherein the OTP element is an anti-fuse constructed from one or more contacts or vias with dielectrics in between.
19. A method for operating an OTP memory comprises:
providing a plurality of OTP cells, at least one of the OTP cells includes at least (i) an OTP element coupled to a first supply voltage line; and (ii) a diode including at least a first active region and a second active region, where the first active region having a first type of dopant and the second region having a second type of dopant, the first active region associated with a first terminal of the diode, the second active region associated with a second terminal of the diode, both the first and second active regions being fabricated from sources or drains of CMOS devices and residing in a common well in CMOS technology, the first active region coupled to the OTP element, and the second active region coupled to a second supply voltage line; and
one-time programming a logic state into at least one of the OTP cells by applying voltages to the first and the second voltage lines,
wherein the first and second active regions are separated by at least one of shallow trench isolation, a dummy CMOS gate, or a silicide block layer.
20. A method as recited in claim 19 , wherein the first and second active regions are separated by at least two of shallow trench isolation, a dummy CMOS gate, or a silicide block layer.