COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
An AlGaN/GaN HEMT includes: an electron transit layer; an electron supply layer formed above the electron transit layer; and a gate electrode formed above the electron supply layer, wherein a p-type semiconductor region is formed only at a site of the electron transit layer which is contained in a region below the gate electrode.
1 . A compound semiconductor device, comprising:
an electron transit layer;
an electron supply layer formed above the electron transit layer; and
an electrode formed above the electron supply layer,
wherein a p-type semiconductor region is formed only at a site of the electron transit layer which is contained in a region below the electrode.
2 . The compound semiconductor device according to claim 1 ,
wherein the p-type semiconductor region is formed narrower in width than the electrode.
3 . The compound semiconductor device according to claim 1 ,
wherein the p-type semiconductor region has an upper surface formed in a surface of the electron transit layer.
4 . The compound semiconductor device according to claim 1 , further comprising:
a spacer layer between the electron transit layer and the electron supply layer.
5 . The compound semiconductor device according to claim 4 ,
wherein the p-type semiconductor region is formed in the electron transit layer and the spacer layer, and
wherein a portion of the spacer layer in the p-type semiconductor region is lower in p-type impurity concentration than a portion of the electron transit layer in the p-type semiconductor region.
6 . The compound semiconductor device according to claim 1 ,
wherein the p-type semiconductor region has an upper surface formed at a site away from the surface of the electron transit layer in a depth direction.
7 . The compound semiconductor device according to claim 1 , further comprising:
a protective layer between the electron supply layer and the electrode.
8 . The compound semiconductor device according to claim 7 , further comprising:
a gate insulating film between the protective layer and the electrode.
9 . A method of manufacturing a compound semiconductor device, comprising:
forming an electron transit layer;
forming a p-type semiconductor region only at an electrode formation scheduled site of the electron transit layer;
forming an electron supply layer above the electron transit layer; and
forming an electrode at a site above the electron supply layer which contains the p-type semiconductor region.
10 . The method of manufacturing a compound semiconductor device according to claim 9 ,
wherein the p-type semiconductor region is formed narrower in width than the electrode.
11 . The method of manufacturing a compound semiconductor device according to claim 9 ,
wherein the p-type semiconductor region has an upper surface formed in a surface of the electron transit layer.
12 . The method of manufacturing a compound semiconductor device according to claim 9 , further comprising:
forming a spacer layer between the electron transit layer and the electron supply layer.
13 . The method of manufacturing a compound semiconductor device according to claim 12 ,
wherein the p-type semiconductor region is formed in the electron transit layer and the spacer layer, and
wherein a portion of the spacer layer in the p-type semiconductor region is lower in p-type impurity concentration than a portion of the electron transit layer in the p-type semiconductor region.
14 . The method of manufacturing a compound semiconductor device according to claim 9 ,
wherein the p-type semiconductor region has an upper surface formed at a site away from the surface of the electron transit layer in a depth direction.
15 . The method of manufacturing a compound semiconductor device according to claim 9 , further comprising:
forming a protective layer between the electron supply layer and the electrode.
16 . A power supply circuit comprising a transformer, and a high-voltage circuit and a low-voltage circuit across the transformer,
the high-voltage circuit comprising a transistor,
the transistor comprising:
an electron transit layer;
an electron supply layer formed above the electron transit layer; and
an electrode formed above the electron supply layer,
wherein a p-type semiconductor region is formed only at a site of the electron transit layer which is contained in a region below the electrode.