Thin film transistor array panel

1. A thin film transistor array panel comprising:

a first gate line and a second gate line extending in a second direction and neighboring each other;

a first data line and a second data line extending in a first direction and neighboring each other; and

a first pixel electrode connected to the first gate line and the first data line through a first thin film transistor,

wherein the first pixel electrode completely covers the first gate line in the first direction and does not cover the second gate line.

2. The thin film transistor array panel of claim 1 , further comprising:

a second pixel electrode connected to the second gate line and the second data line through a second thin film transistor,

wherein the second pixel electrode completely covers the second gate line in the first direction and does not cover the second gate line.

3. The thin film transistor array panel of claim 2 , wherein the first pixel electrode and the second pixel electrode are located in a region surrounded by the first gate line, the second gate line, the first data line and the second data line.

4. The thin film transistor array panel of claim 1 , wherein the first pixel electrode and a second pixel electrode are located in a region surrounded by the first gate line, the second gate line, the first data line and the second data line.

5. A thin film transistor array panel comprising:

a first gate line and a second gate line extending in a second direction and neighboring each other;

a first data line and a second data line extending in a first direction and neighboring each other; and

a first pixel electrode connected to the first gate line and the first data line through a first thin film transistor,

wherein the second gate line is applied with a gate-on voltage before the first gate line and is disposed in a previous row of the first gate line, and

wherein the first pixel electrode completely covers the first gate line in the first direction and covers at least a portion of the second gate line in the first direction.

6. The thin film transistor array panel of claim 5 , further comprising:

a third gate line and a fourth gate line extending in the second direction and neighboring each other; and

a second pixel electrode connected to the third gate line and the second data line through a second thin film transistor,

wherein the fourth gate line is applied with a gate-on voltage after the third gate line and is disposed in a subsequent row of the third gate line, and

wherein the second pixel electrode completely covers the third gate line in the first direction.

7. The thin film transistor array panel of claim 6 , wherein the first pixel electrode and the second pixel electrode are located in a region surrounded by the first gate line, the third gate line, the first data line and the second data line.

8. The thin film transistor array panel of claim 7 , wherein the second pixel electrode does not cover the fourth gate line.

9. The thin film transistor array panel of claim 6 , wherein the second pixel electrode does not cover the fourth gate line.

10. The thin film transistor array panel of claim 5 , further comprising:

a third gate line and a fourth gate line extending in the second direction and neighboring each other; and

a second pixel electrode connected to the third gate line and the second data line through a second thin film transistor,

wherein the first pixel electrode and the second pixel electrode are located in a region surrounded by the first gate line, the third gate line, the first data line and the second data line.

11. The thin film transistor array panel of claim 10 , wherein the second pixel electrode does not cover the fourth gate line.

12. The thin film transistor array panel of claim 5 , further comprising:

a third gate line and a fourth gate line extending in the second direction and neighboring each other; and

a second pixel electrode connected to the third gate line and the second data line through a second thin film transistor,

wherein the second pixel electrode does not cover the fourth gate line.

13. A thin film transistor array panel comprising:

a plurality of pixel electrodes arranged in a matrix;

a plurality of gate lines extending in a second direction, wherein a pair of gate lines is disposed for one pixel electrode row; and

a plurality of data lines extending in a first direction such that one of the data lines is disposed for two pixel electrode columns,

wherein the pair of gate lines disposed at each pixel electrode row include the first gate line and the second gate line neighboring each other,

each pixel electrode row includes a first pixel electrode connected to the first gate line and a second pixel electrode connected to the second gate line,

the first pixel electrode covers the first gate line in the first direction and does not cover the second gate line, and

the second pixel electrode covers the second gate line in the first direction and does not cover the first gate line.

14. The thin film transistor array panel of claim 13 , wherein

the first pixel electrode of one pixel electrode row covers the second gate line of a previous pixel electrode row in the first direction.

15. The thin film transistor array panel of claim 14 , wherein

the first gate line connected to the first pixel electrode of one pixel electrode row is applied with a gate-on voltage later than the second gate line of the previous pixel electrode row.

16. The thin film transistor array panel of claim 13 , wherein

the second pixel electrode of one pixel electrode row covers the first gate line of the corresponding pixel electrode row in the first direction.

17. The thin film transistor array panel of claim 13 , wherein the second pixel electrode does not cover the first gate line.