Semiconductor device manufacturing method
View Patent ↗In a process of dividing gates of multi-layered films in fabricating a NAND flash memory having a three-dimensional structure, a pattern is prevented from deforming and falling. A ratio of a length L to a height h of control gate groups configuring a memory cell of the flash memory is set to be less than 1.65 which is a range in which buckling does not occur. It is desirable that a ratio of a length L to a width W of the control gate groups is set to be less than 16.5.
1. A semiconductor device manufacturing method comprising the step of forming a three-dimensional memory cell,
the step of forming a three-dimensional memory cell comprising the steps of:
stacking a plurality of control gate layers, each of which is configured as a multi-layered film of an insulating layer and a conductor layer;
forming channel holes in the plurality of stacked control gate layers; and
forming a plurality of control gate groups by forming trenches in the plurality of stacked control gate layers by plasma etching to separate the plurality of stacked control gate layers,
wherein a length in a longitudinal direction and a height of the control gate groups are determined so that a value obtained by dividing a buckling cycle by the height becomes a value with which buckling does not occur, the buckling cycle being obtained by dividing twice the length by a natural number.
2. The method according to claim 1 , wherein a value obtained by dividing the height of the control gate groups by a width in a short-side direction of the control gate groups is 10 or more.
3. The method according to claim 1 , wherein the length divided by the height is less than 1.65.
4. The method according to claim 3 , wherein a ratio of the length to a width in a short-side direction of the control gate groups defined by the trenches is less than 16.5.
5. The method according to claim 4 , wherein a plurality of rows of the channel holes are formed in the control gate groups.
6. The method according to claim 1 , wherein:
the control gate groups are formed to have a stepwise shape in which a length of an upper control gate layer is smaller than a length of a lower control gate layer, and
length the height of the control gate groups are defined as a length of a lowermost control gate layer of the stepwise shape and an overall height of the stepwise shape, respectively.
7. The method according to claim 1 , wherein the step of forming a plurality of control gate groups comprises the steps of:
forming a line-and-space pattern on the plurality of stacked control gate layers; and
etching the plurality of stacked control gate layers to the lowermost layer with the line-and-space pattern used as a mask, and
wherein the line-and-space pattern has a shape in which individual patterns are waving in a same phase as each other and the channel holes are positioned in positions of inflection points of waviness.
8. The method according to claim 1 , wherein the value with which buckling does not occur is smaller than 3.3.
9. The method according to claim 2 , wherein the value obtained by dividing the height by the width is less than 1.65.
10. A semiconductor device manufacturing method comprising the step of forming a three-dimensional memory cell,
the step of forming a three-dimensional memory cell comprising the steps of:
stacking a plurality of control gate layers, each of which is configured as a multi-layered film of an insulating layer and a conductor layer;
forming channel holes in the plurality of stacked control gate layers; and
forming a plurality of control gate groups by forming trenches in the plurality of stacked control gate layers by plasma etching to separate the plurality of stacked control gate layers,
wherein a length in a longitudinal direction and a height of the control gate groups are determined so that a value obtained by dividing a buckling cycle by the height becomes a value with which buckling does not occur, the buckling cycle being obtained by dividing twice the length by a natural number, and
wherein the step of forming a plurality of control gate groups comprises the steps of:
forming a line-and-space pattern on the plurality of stacked control gate layers; and
etching the plurality of stacked control gate layers to the lowermost layer with the line-and-space pattern used as a mask,
wherein the line-and-space pattern has a shape in which individual patterns are waving in a same phase as each other and the channel holes are positioned in positions of inflection points of waviness.