Error detection or correction of a portion of a codeword in a memory device

1. A method of retrieving data, the method comprising:

receiving a read access request from a requesting agent targeting a particular sub-codeword of a codeword stored in a memory array, wherein the codeword comprises a plurality of sub-codewords and parity bits, and wherein each sub-codeword of the codeword comprises sub-codeword data and corresponding error detection code bits;

in response to the read access request:

reading only the particular sub-codeword and the corresponding error detection code;

performing an error detection operation only on the read particular sub-codeword, using the read error detection code bits of the read particular sub-codeword, wherein the error detection operation is performed without reading the codeword as a whole from the memory array;

transmitting only the read particular sub-codeword to the requesting agent, at least in part in response to not detecting an error in the read particular sub-codeword, without performing the error detection and correction operation on the codeword as a whole and without transmitting the whole codeword to the requesting agent;

reading the whole codeword and the parity bits only in response to detecting an error in the read particular sub-codeword and determining that the whole codeword is available for reading;

performing an error detection and correction operation on the read codeword as a whole based on the read parity bits, such that the read particular sub-codeword is corrected; and

transmitting only the corrected particular sub-codeword to the requesting agent without transmitting the whole codeword to the requesting agent;

receiving a write request targeting the particular sub-codeword to program information into a location in the memory array allocated to the particular sub-codeword in accordance with the write request;

in response to the write request:

determining whether the parity bits are available;

reading the sub-codeword data of the particular sub-codeword, the error detection code bits of the particular sub-codeword, and the parity bits responsive to the parity bits being available to be read;

generating new error detection code bits for the particular sub-codeword from the information;

generating new parity bits associated with the codeword based on the read parity bits and the information; and

programming the information and the new error detection code bits into the location in the memory array allocated to the particular sub-codeword and programming the new parity bits into the memory array.

2. The method of claim 1 , wherein transmitting only the read particular sub-codeword to the requesting agent comprises transmitting only the read particular sub-codeword to an input/output interface.

3. The method of claim 1 , further comprising providing the corrected particular sub-codeword to an input/output interface and transmitting the corrected particular sub-codeword from the input/output interface to the requesting agent to satisfy the read access request.

4. The method of claim 1 , further comprising waiting until the whole codeword is available for reading prior to reading the whole codeword and the parity bits.

5. The method of claim 1 , wherein performing the error detection operation on the read particular sub-codeword using the read error detection code bits of the read particular sub-codeword comprises performing a cyclic redundancy check of the read particular sub-codeword, wherein the read error detection code bits of the read particular sub-codeword comprise one or more data bits and one or more cyclic redundancy check bits.

6. The method of claim 1 , wherein performing the error detection and correction operation on the read codeword as a whole based on the read parity bits comprises performing the error detection and correction operation on the read codeword as a whole based on respective states of the read parity bits.

7. The method of claim 1 , wherein the memory array comprises phase change memory (PCM).

8. A memory device comprising:

a memory array configured to store a codeword comprising a plurality of sub-codewords and one or more parity bits, wherein each sub-codeword of the plurality of sub-codewords comprises a particular amount of user data and a corresponding error detection code; and

a controller configured to, in response to receiving a read access request from a requesting agent targeting only a particular sub-codeword of the plurality of sub-codewords:

read only the particular sub-codeword and the corresponding error detection code;

perform an error detection operation only on the read particular sub-codeword, using the read error detection code of the read particular sub-codeword, wherein the error detection operation performed is performed without reading the codeword as a whole from the memory array;

transmit only the read particular sub-codeword to the requesting agent, at least in part in response to not detecting an error in the read particular sub-codeword, without performing the error detection and correction operation on the codeword as a whole and without transmitting the whole codeword to the requesting agent;

read the whole codeword and the one or more parity bits only in response to detecting an error in the read particular sub-codeword and determining that the whole codeword is available for reading;

perform an error detection and correction operation on the read codeword as a whole based on the read one or more parity bits such that the read particular sub-codeword is corrected; and

transmit the only the corrected particular sub-codeword to the requesting agent without transmitting the whole codeword to the requesting agent.

9. The memory device of claim 8 , further comprising an input/output interface configured to transmit the corrected particular sub-codeword to the requesting agent to fulfill the read access request.

10. The memory device of claim 8 , wherein the controller is configured to read the whole codeword and the one or more parity bits, at least in part, by waiting until the whole codeword is available for reading.

11. The memory device of claim 10 , wherein the controller is further configured to perform the error detection operation on the read particular sub-codeword using the read error detection code of the read particular sub-codeword, at least in part, by performing a cyclic redundancy check on the read particular sub-codeword, wherein the read error detection code of the read particular sub-codeword comprises one or more data bits and one or more cyclic redundancy check bits.

12. The memory device of claim 11 , wherein the controller is further configured to perform the error detection and correction operation on the read codeword as a whole based on the one or more read parity bits by performing the error detection and correction operation on the read codeword as a whole based, at least in part, on respective states of the read one or more parity bits.

13. The memory device of claim 8 , wherein the non-volatile memory device comprises a phase change memory (PCM) device.

14. A system comprising:

a master controller; and

one or more non-volatile memory devices coupled to the master controller, wherein the one or more non-volatile memory devices individually comprise:

a memory array configured to store a codeword comprising a plurality of sub-codewords and parity bits wherein each sub-codeword of the codeword comprises sub-codeword data and corresponding error detection code bits; and

a local controller configured to in response to receiving a read access request from a requesting agent targeting only a particular sub-codeword of the plurality of sub-codewords:

read only the particular sub-codeword and the corresponding error detection code;

perform an error detection operation only on the read particular sub-codeword, using the error detection code bits of the particular sub-codeword, at least in part in response to the read access request targeting the particular sub-codeword, wherein the error detection operation is performed without reading the codeword as a whole from the memory array;

transmit only the read particular sub-codeword to the requesting agent, at least in part in response to not detecting an error in the read particular sub-codeword, without performing the error detection and correction operation on the codeword as a whole and without transmitting the whole codeword to the requesting agent;

read the whole codeword and the parity bits only in response to detecting an error in the read particular sub-codeword and determining that the whole codeword is available for reading;

perform an error detection and correction operation on the read codeword as a whole based on the read parity bits such that the read particular sub-codeword is corrected;

transmit only the corrected particular sub-codeword to the requesting agent without transmitting the whole codeword to the requesting agent;

wherein the local controller is configured to receive a write request targeting the particular sub-codeword to program information into a location in the memory array allocated to the particular sub-codeword in accordance with the write request;

wherein the local controller is configured to in response to receiving the write request:

determine whether the parity bits are available to be read;

read the sub-codeword data of the particular sub-codeword, the error detection code bits of the particular sub-codeword, and the parity bits responsive to the parity bits being available to be read;

generate new error detection code bits for the particular sub-codeword from the information;

generate new parity bits associated with the codeword based on the read parity bits and the information; and

program the information and the new error detection code bits into the location in the memory array allocated to the particular sub-codeword and program the new parity bits into the memory array.

15. The system of claim 14 , wherein the one or more of the plurality of non-volatile memory devices individually further comprising an input/output interface configured to transmit the corrected particular sub-codeword to the master controller to fulfill the read access request.

16. The system of claim 14 , wherein the local controller is further configured to wait until the whole codeword is available for reading prior to reading the whole codeword and the parity bits.

17. The system of claim 14 , wherein the local controller is further configured to perform the error detection operation on the read particular sub-codeword using the read error detection code bits of the read particular sub-codeword, at least in part, by performing a cyclic redundancy check of the read particular sub-codeword, wherein the read error detection code bits of the read particular sub-codeword comprises one or more data bits and one or more cyclic redundancy check bits.

18. The system of claim 14 , wherein the local controller is further configured to perform the error detection and correction operation on the read codeword as a whole based on the read parity bits by performing the error detection and correction operation on the read codeword as a whole based, at least in part, on respective states of the read parity bits.

19. The system of claim 14 , wherein the system comprises a solid state drive.

20. The system of claim 14 , wherein the one or more non-volatile memory devices comprise phase change memory (PCM) devices.