Sub-block accessible nonvolatile memory cache

1. An electronically-implemented method of managing memory, the method comprising:

counting at least one of a quantity or frequency of read commands to read a particular information to generate a count, wherein the particular information is stored at least in a non-sub-block accessible memory; and

storing the count.

2. The method of claim 1 , wherein the non-sub-block accessible memory is not byte-addressable.

3. The method of claim 1 , wherein storing the count further comprises storing the count in a sub-block accessible memory.

4. The method of claim 1 , further comprising retrieving the particular information from a non-volatile cache using a sub-block accessible address associated with the particular information.

5. The method of claim 1 , further comprising determining whether the particular information is stored in a non-volatile cache by discretely addressing the cache to search for the particular information.

6. The method of claim 1 , further comprising:

determining whether the particular information is stored in a non-volatile cache; and

if the particular information is not stored in the non-volatile cache, determining whether to store the particular information in the non-volatile cache, wherein determining is based, at least in part, on a user request to permanently cache the particular information.

7. The method of claim 1 , further comprising:

determining whether the particular information is stored in a non-volatile cache; and

if the particular information is not stored in the non-volatile cache, retrieving the particular information from the non-sub-block accessible nonvolatile memory.

8. The method of claim 1 , wherein the non-sub-block accessible memory comprises NAND flash memory.

9. An apparatus comprising a memory controller, the apparatus comprising:

an interface configured to communicate with at least a cache memory and a non-sub-block accessible memory;

electronic circuitry configured to:

count at least one of a quantity or frequency of read commands to read a particular information to generate a count, wherein the particular information is stored at least in the non-sub-block accessible memory; and

cause the count to be stored.

10. The apparatus of claim 9 , wherein the non-sub-block accessible memory is not byte-addressable.

11. The apparatus of claim 9 , wherein the electronic circuitry is further configured to store the count in a sub-block accessible memory.

12. The apparatus of claim 9 , wherein the electronic circuit is further configured to retrieve the particular information from a non-volatile cache using a sub-block accessible address associated with the particular information.

13. The apparatus of claim 9 , wherein the electronic circuit is further configured to determine whether the particular information is stored in a non-volatile cache by discretely addressing the cache to search for the particular information.

14. The apparatus of claim 9 , wherein the electronic circuit is further configured to:

determine whether the particular information is stored in a non-volatile cache; and

if the particular information is not stored in the non-volatile cache, determine whether to store the particular information in the non-volatile cache, wherein determining is further based, at least in part, on a user request to permanently cache the said particular information.

15. The apparatus of claim 9 , wherein the electronic circuit is further configured to:

determine whether the particular information is stored in a non-volatile cache; and

if the particular information is not stored in the non-volatile cache, retrieve the particular information from the non-sub-block accessible nonvolatile memory.

16. The apparatus of claim 9 , wherein the non-sub-block accessible memory comprises NAND flash memory.

17. A system comprising:

a memory device comprising a non-sub-block accessible memory and a non-volatile cache;

a memory controller configured to:

count at least one of a quantity or frequency of read commands to read a particular information to generate a count, wherein the particular information is stored at least in the non-sub-block accessible memory;

cause the count to be stored; and

a processor configured to host one or more applications and to initiate the read command to the memory controller.

18. The system of claim 17 , wherein the memory controller is further configured to if the particular information is not stored in the non-volatile cache, determine whether to store the particular information in the non-volatile cache based at least in part on the count.

19. The system of claim 17 , wherein the count is maintained in the non-sub-block accessible nonvolatile memory.

20. The apparatus of claim 17 , wherein the non-sub-block accessible memory comprises NAND flash memory.