Self-aligned thin film transistor with doping barrier and method of manufacturing the same
View Patent ↗Disclosed are a self-aligned thin film transistor controlling a diffusion length of a doping material using a doping barrier in a thin film transistor having a self-aligned structure and a method of manufacturing the same. The self-aligned thin film transistor with a doping barrier includes: an active layer formed on a substrate and having a first doping region, a second doping region, and a channel region; a gate insulating film formed on the channel region; a gate electrode formed on the gate insulating film; a doping source film formed on the first doping region and the second doping region; and a doping barrier formed between the doping source film and the first doping region and between the doping source film and the second doping region.
1. A self-aligned thin film transistor with a doping barrier, comprising:
a substrate;
an active layer on the substrate and having a first doped region, a second doped region, and a channel region, the first doped region being a source region and the second doped region being a drain region;
a gate insulating film on the channel region;
a gate electrode on the gate insulating film;
a doping source film including first and second doping source film portions respectively on the first doped region and the second doped region;
a doping barrier including
a first doping barrier portion between the first doping source film portion and the first doped region, the first doping barrier portion being formed to delay diffusion and control an amount of doping materials diffusing from the first doping source film portion when forming the first doped region, and
a second doping barrier portion between the second doping source film portion and the second doped region, the second doping barrier portion being formed to delay diffusion and control an amount of doping materials diffusing from the second doping source film portion when forming the second doped region; and
source and drain electrodes provided so as to be electrically connected to the source and drain regions via the doping source film,
wherein the first doping barrier portion and the first doped region are formed between the substrate and the source electrode,
wherein the second doping barrier portion and the second doped region are formed between the substrate and the drain electrode, and
wherein the gate insulating film is different from the first doping barrier portion and the second doping barrier portion.
2. The self-aligned thin film transistor of claim 1 , further comprising an interlayer insulating film on the first and second doping source film portions and the gate electrode, and having a first contact hole and a second contact hole, wherein
the source electrode is disposed on the interlayer insulating film and in the first contact hole to be connected with the source region; and
the drain electrode is disposed on the interlayer insulating film and in the second contact hole to be connected with the drain region.
3. The self-aligned thin film transistor of claim 1 , wherein the gate insulating film is directly under the gate electrode, and the first and second doped regions are directly under the first and second doping barrier portions, respectively, so that all of each of the first and second doped regions is disposed laterally with respect to the gate electrode.
4. The self-aligned thin film transistor of claim 1 , wherein the source and drain electrodes are respectively electrically connected to the source and drain regions through the doping source film.
5. The self-aligned thin film transistor of claim 4 , wherein the doping source film is interposed between the source region and the source electrode, and
further wherein the doping source film is interposed between the drain region and the drain electrode.
6. The self-aligned thin film transistor of claim 5 , wherein the doping barrier is interposed between the source region and the source electrode, and
further wherein the doping barrier is interposed between the drain region and the drain electrode.
7. The self-aligned thin film transistor of claim 4 , wherein the source electrode and the drain electrode are free of any direct contact with the source and drain regions.
8. The self-aligned thin film transistor of claim 1 , wherein all of a bottom surface of the gate insulating film is in direct contact with the channel region.
9. A self-aligned thin film transistor with a doping barrier, comprising:
a substrate;
an active layer on the substrate and having a first doped region, a second doped region, and a channel region, the first doped region being a source region and the second doped region being a drain region;
a gate insulating film on the channel region;
a gate electrode on the gate insulating film;
a doping source film on the first doped region and the second doped region; a doping barrier between the doping source film and the first doped region and between the doping source film and the second doped region; and
source and drain electrodes provided so as to be electrically connected to the source and drain regions via the doping source film,
wherein the gate insulating film is directly under the gate electrode, and the first and second doped regions are both directly under the doping barrier so that all of each of the first and second doped regions is disposed laterally with respect to the gate electrode,
wherein a first doping barrier portion of the doping barrier, and the first doped region are formed between the substrate and the source electrode,
wherein a second doping barrier portion of the doping barrier, and the second doped region are formed between the substrate and the drain electrode, and
wherein the gate insulating film is different from the first doping barrier portion and the second doping barrier portion.
10. The self-aligned thin film transistor of claim 9 , the source and drain electrodes are respectively electrically connected to the source and drain regions through the doping source film.
11. The self-aligned thin film transistor of claim 10 , wherein the doping source film is interposed between the source region and the source electrode, and
further wherein the doping source film is interposed between the drain region and the drain electrode.
12. The self-aligned thin film transistor of claim 11 , wherein the doping barrier is interposed between the source region and the source electrode, and
further wherein the doping barrier is interposed between the drain region and the drain electrode.
13. The self-aligned thin film transistor of claim 10 , wherein the drain and source electrodes are free of any direct contact with the source and drain regions.
14. The self-aligned thin film transistor of claim 9 , wherein all of a bottom surface of the gate insulating film is in direct contact with the channel region.