IP Library Granted Patent US 8,860,075
Granted Patent B2
US 8,860,075 · App. 13/962,643 · Granted Oct 14, 2014

Semiconductor light emitting device

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Quick Facts
Patent No.
US 8,860,075
App. No.
13/962,643
Granted
Oct 14, 2014
Kind
B2
Abstract

According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, a p-side metal pillar, an n-side metal pillar, and an insulator. The semiconductor layer includes a first surface, a second surface opposite to the first surface, and a light emitting layer. The p-side metal pillar includes a p-side external terminal. The n-side metal pillar includes an n-side external terminal. At least one selected from an area and a planar configuration of the p-side external terminal is different from at least one selected from an area and a planar configuration of the n-side external terminal.

Claims (45)

1. A semiconductor light emitting device, comprising:

a semiconductor layer including a first surface, a second surface opposite to the first surface, and a light emitting layer provided between the first surface and the second surface;

a p-side electrode provided on the semiconductor layer;

an n-side electrode provided on the semiconductor layer;

a p-side metal pillar provided on the second surface side, and electrically connected to the p-side electrode;

an n-side metal pillar provided apart from the p-side metal pillar on the second surface side, and electrically connected to the n-side electrode; and

an insulator provided at least between the p-side metal pillar and the n-side metal pillar,

the p-side metal pillar including a p-side external terminal exposed from the insulator at a surface different from a surface connected to the p-side electrode, and

the n-side metal pillar including an n-side external terminal exposed from the insulator at a surface different from a surface connected to the n-side electrode, wherein

one selected from the p-side external terminal and the n-side external terminal is formed in a first configuration of a quadrilateral, and

another selected from the p-side external terminal and the n-side external terminal is formed in a second configuration, the second configuration being a configuration without a corner of a quadrilateral having same exterior size and exterior configuration as the first configuration.

2. The device of claim 1 , wherein the n-side external terminal is exposed from the insulator at a surface which faces a same direction as the surface where the p-side external terminal is exposed.

3. The device of claim 1 , wherein the area of the p-side external terminal is greater than the area of the n-side external terminal.

4. The device of claim 1 , wherein the p-side external terminal is formed in the first configuration and the n-side external terminal is formed in the second configuration.

5. The device of claim 1 , wherein the insulator covers all side surfaces of the p-side metal pillar and the n-side metal pillar.

6. The device of claim 1 , further comprising:

an insulating layer provided on the second surface side, the insulating layer having a first via communicating with the p-side electrode and a second via communicating with the n-side electrode;

a p-side interconnect layer provided at least inside the first via, and electrically connected to the p-side electrode; and

an n-side interconnect layer provided apart from the p-side interconnect layer inside the second via and on an interconnect surface of the insulating layer, the interconnect surface opposite to the semiconductor layer, the n-side interconnect layer being electrically connected to the n-side electrode,

the p-side metal pillar being provided on a surface of the p-side interconnect layer on a side opposite to a portion contacting the first via,

the n-side metal pillar being provided on a surface of the n-side interconnect layer on a side opposite to a portion contacting the second via.

7. The device of claim 6 , wherein an area of the p-side interconnect layer is greater than the area of the p-side external terminal.

8. The device of claim 6 , wherein an area of the n-side interconnect layer is greater than an area of the n-side electrode.

9. The device of claim 6 , wherein the first via is provided in a plurality and the p-side interconnect layer is connected to the p-side electrode via the plurality of the first vias.

10. The device of claim 6 , wherein the p-side metal pillar is thicker than the p-side interconnect layer.

11. The device of claim 6 , wherein the n-side metal pillar is thicker than the n-side interconnect layer.

12. The device of claim 6 , wherein a distance between the p-side external terminal and the n-side external terminal is greater than a distance between the p-side interconnect layer and the n-side interconnect layer.

13. The device of claim 1 , further comprising a transparent body provided on the first surface, the transparent body being transparent to light emitted from the light emitting layer.

14. The device of claim 13 , wherein the transparent body includes a transparent resin and a phosphor dispersed in the transparent resin.

15. The device of claim 1 , wherein a substrate is not provided on the first surface side, and a transparent body is provided on the first surface side without a substrate being interposed between the transparent body and the semiconductor layer.

16. The device of claim 1 , wherein the semiconductor layer is formed on a substrate, and the substrate is removed from the semiconductor layer.

17. The device of claim 16 , wherein the semiconductor layer is a crystal growth layer using the substrate.

18. The device of claim 1 , wherein the semiconductor layer had been formed on a substrate.

19. The device of claim 1 , wherein the p-side external terminal has an end portion to be connected to a mounting member, and the n-side external terminal has an end portion to be connected to the mounting member.

20. A semiconductor light emitting device, comprising:

a semiconductor layer including a first surface, a second surface opposite to the first surface, and a light emitting layer provided between the first surface and the second surface;

a p-side electrode provided on the semiconductor layer;

an n-side electrode provided on the semiconductor layer;

a p-side metal pillar provided on the second surface side, and electrically connected to the p-side electrode;

an n-side metal pillar provided apart from the p-side metal pillar on the second surface side, and electrically connected to the n-side electrode; and

an insulator provided at least between the p-side metal pillar and the n-side metal pillar,

the p-side metal pillar including a p-side external terminal exposed from the insulator at a surface different from a surface connected to the p-side electrode, and

the n-side metal pillar including an n-side external terminal exposed from the insulator at a surface different from a surface connected to the n-side electrode, wherein

at least one selected from an area and a planar configuration of the p-side external terminal being different from at least one selected from an area and a planar configuration of the n-side external terminal, and

an exterior form of a mounting surface including the p-side external terminal and the n-side external terminal being formed in a rectangular configuration, and the p-side external terminal and the n-side external terminal being disposed symmetrically around a center line dividing a longitudinal direction of the rectangular configuration into two equal parts.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 30, 2018
From: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 046986/0159 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 14, 2018
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
Reel/Frame 046364/0164 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 8, 2013
From: IZUKA, MIYUKI; OBATA, SUSUMU; KIMURA, AKIYA; KOJIMA, AKIHIRO; AKIMOTO, YOSUKE; SUGIZAKI, YOSHIAKI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 030972/0805 →