Nonvolatile semiconductor memory device

1. A nonvolatile semiconductor memory device comprising:

memory cells each of which stores data with two or more levels, each of the memory cells including a semiconductor layer, a first insulating layer on the semiconductor layer, a charge storage layer on the first insulating layer, a second insulating layer on the charge storage layer, and a control gate electrode on the second insulating layer, and the second insulating layer including a ferroelectric layer; and

a control circuit which is configured to:

apply a first pulse voltage having a first voltage value and a first pulse width to the control gate electrode in a write mode in which charges are stored in the charge storage layer, and

apply a second pulse voltage to the control gate electrode in a read mode in which a charge amount in the charge storage layer is judged,

wherein the second pulse voltage has a first period and a second period after the first period,

wherein the second period has a read voltage value to judge the charge amount in the charge storage layer, and

wherein the first period has a second voltage value larger than the read voltage value and a polarization arrangement pulse voltage having a second pulse width narrower than the first pulse width.

2. The device of claim 1 , wherein the second voltage value is smaller than the first voltage value.

3. The device of claim 1 , wherein the second pulse width is larger than 10 nsec and not more than 1/20 of the first pulse width, and the second voltage value is larger than the first voltage value.

4. The device of claim 3 , wherein the ferroelectric layer includes HfO 2 doped with Si, and the second pulse width is less than 100 nsec.

5. The device of claim 4 , wherein the second insulating layer comprises a TiN layer arranged on at least one of an upper surface and a lower surface of the ferroelectric layer.

6. The device of claim 1 , wherein the first period and the second period are continuous.

7. The device of claim 1 , wherein each of the memory cells stores data with 2 n (n is a natural number not less than 2) levels.

8. The device of claim 7 , wherein the read voltage value includes (2 n-1 ) different read voltage values.

9. The device of claim 1 , further comprising a NAND string in which the memory cells are connected in series.

10. The device of claim 9 , wherein the control circuit applies the second pulse voltage to the control gate electrode of a selected memory cell among the memory cells in the read mode.

11. The device of claim 10 , wherein the control circuit applies a third pulse voltage to the control gate electrode of an unselected memory cell among the memory cells.

12. The device of claim 11 , wherein the third pulse voltage has the first period and a third period after the first period, and the third period has a transfer voltage value larger than the read voltage value.

13. The device of claim 12 , wherein the transfer voltage value is smaller than the second voltage value.

14. The device of claim 13 , wherein the first period has the transfer voltage value before the polarization arrangement pulse voltage.

15. The device of claim 1 , wherein the read mode includes a verify read mode in which the charges stored in the charge storage layer in the write mode are verified.

16. The device of claim 1 , wherein the ferroelectric layer includes HfO 2 doped with Y.

17. The device of claim 16 , wherein the second insulating layer comprises a TiN layer arranged on at least one of an upper surface and a lower surface of the ferroelectric layer.

18. The device of claim 1 , wherein the ferroelectric layer includes one material selected from a group of SBT, PZT, BLT, and BST.

19. The device of claim 18 , wherein the second insulating layer comprises a conductive oxide layer arranged on at least one of an upper surface and a lower surface of the ferroelectric layer.