Semiconductor memory device
Disclosed is a semiconductor memory device that includes a late write register for temporarily storing a late write address and late write data. When a write command is input, the semiconductor memory device performs a dummy read, creates a data set having a predetermined bit width from data read by the dummy read and write data, and generates a correction bit from the data set. In parallel with the generation of the data set and the generation of the correction bit, the semiconductor memory device not only performs a late write to write the late write data at the late write address in the memory core, but also stores a write address in the late write register as a new late write address and stores the data set and the correction bit in the late write register as new late write data.
1. A semiconductor memory device comprising:
a memory core;
a correction bit generation circuit that generates a correction bit from data having a predetermined bit width;
a data set generation section;
a late write register that temporarily stores a late write address and late write data; and
a control section that exercises control in compliance with a write command for write data having a bit width less than the predetermined bit width in order to perform a dummy read operation, a data set generation process, a correction bit generation process, a late write operation, and a late write data storage process;
wherein the dummy read operation is performed to output data corresponding to a write address of the write command from the memory core;
wherein the data set generation process is performed by the data set generation section to generate a data set having the predetermined bit width by using the data output from the memory core during the dummy read operation to add bits in order to compensate for the shortfall in the write data;
wherein the correction bit generation process is performed by the correction bit generation circuit to generate the correction bit from the data set;
wherein the late write operation is performed in parallel with the generation of the data set and of the correction bit to write the late write data stored in the late write register into a memory cell of the memory core that corresponds to the late write address; and
wherein the late write data storage process is performed to handle the write address as a new late write address and store the data set and the correction bit into the late write register as new late write data.
2. The semiconductor memory device according to claim 1 , further comprising:
a read circuit that compares a read address to the late write address stored in the late write register when a read command is input;
wherein, if the read address coincides with the late write address, the read circuit outputs the data set included in the late write data stored in the late write register; and
wherein, if the read address does not coincide with the late write address, the read circuit not only reads data with the correction bit from the read address in the memory core, but also performs an error correction process on the read data in accordance with the correction bit and outputs the error-corrected data.
3. The semiconductor memory device according to claim 1 , wherein the write command is input in synchronism with a clock; and wherein the control section exercises control so that the dummy read is performed in synchronism with the clock, and that the late write is not performed in synchronism with the clock but is performed subsequently to the dummy read.
4. The semiconductor memory device according to claim 1 , wherein the write command is input in synchronism with the clock; and wherein the write data of the write command is input one cycle later than the write command in synchronism with the clock.
5. The semiconductor memory device according to claim 1 , further comprising:
a refresh control section that exercises control so that the memory core is refreshed at intervals of a plurality of cycles of a clock;
wherein the read command and the write command are input in synchronism with the clock;
wherein the refresh control section exercises control so that the refresh is not performed in synchronism with the clock but is performed subsequently to access to the memory core that is gained in response to the read command or access to the memory core that is gained for the dummy read; and
wherein, when the read command or the write command is input in a cycle subsequent to a cycle in which the refresh is started, the control section delays the start of access to the memory core that is gained in response to the read command or the start of access to the memory core that is gained for the dummy read in response to the write command by a predefined period of time in the subsequent cycle.
6. The semiconductor memory device according to claim 1 , further comprising:
a refresh control section that exercises control so that the memory core is refreshed at intervals of a plurality of cycles of a clock;
wherein data is input and output in burst mode;
wherein the read command and the write command are input in synchronism with the clock;
wherein the refresh control section exercises control so that the refresh is not performed in synchronism with the clock but is performed subsequently to access to the memory core that is gained in response to the read command or access to the memory core that is gained for the dummy read; and
wherein, when the refresh is performed subsequently to the access to the memory core that is gained for the dummy read, the control section delays the start of the late write performed in a cycle subsequent to the dummy read by a predefined period of time in the subsequent cycle.