III-nitride semiconductor device with stepped gate
A III-nitride heterojunction power semiconductor device that includes a passivation body with a gate well having a top mouth that is wider than the bottom mouth thereof, and a method of fabrication for the same.
1. A III-nitride semiconductor device comprising:
a first III-nitride body having one band gap, and a second III-nitride body having another band gap disposed over said first III-nitride body;
a first insulation body situated over said second III-nitride body, and a second insulation body situated over said first insulation body;
a gate well having a first mouth defined in said first insulation body;
a stepped gate arrangement disposed at least partially within said gate well, said stepped gate arrangement including a gate dielectric formed along said first mouth, and a gate electrode over said gate dielectric, said gate dielectric and said gate electrode extending beyond said first mouth.
2. The III-nitride semiconductor device of claim 1 , further comprising a drain electrode and a source electrode on respective sides of said stepped gate arrangement.
3. The III-nitride semiconductor device of claim 1 , wherein said first insulation body comprises silicon nitride.
4. The III-nitride semiconductor device of claim 1 , wherein said second insulation body comprises a nitride dielectric.
5. The III-nitride semiconductor device of claim 1 , wherein said second insulation body comprises silicon nitride.
6. The III-nitride semiconductor device of claim 1 , wherein said second insulation body comprises aluminum nitride.
7. The III-nitride semiconductor device of claim 1 , wherein said first III-nitride body comprises GaN and said second III-nitride body comprises AlGaN.
8. A method of fabricating a III-nitride semiconductor device, said method comprising:
forming a first III-nitride body having one band gap, and a second III-nitride body having another band gap disposed over said first III-nitride body;
forming a first insulation body over said second III-nitride body;
forming a second insulation body situated over said first insulation body;
forming a gate well having a first mouth defined by first and second ledges in said first insulation body, each of said first and second ledges including an exposed top surface portion of said first insulation body;
forming a gate dielectric along said first mouth, said gate dielectric extending beyond said first mouth to cover said exposed top surface portions of said first insulation body;
forming a gate electrode over said gate dielectric, said gate electrode extending beyond said first mouth.
9. The method of claim 8 , further comprising forming a drain electrode and a source electrode on respective sides of said gate electrode.
10. The method of claim 8 , wherein said first insulation body comprises silicon nitride.
11. The method of claim 8 , wherein said second insulation body comprises a nitride dielectric.
12. The method of claim 8 , wherein said second insulation body comprises silicon nitride.
13. The method of claim 8 , wherein said second insulation body comprises aluminum nitride.
14. The method of claim 8 , wherein said first III-nitride body comprises GaN and said second III-nitride body comprises AlGaN.