Interconnection of semiconductor device with graphene wire

1. A semiconductor device comprising:

a substrate having semiconductor elements formed therein,

a first multi-layered graphene wire formed above the substrate, the first multi-layered graphene wire including a multi-layered graphene layer having a preset impurity doped therein,

a second multi-layered graphene wire formed on the same layer as the first multi-layered graphene wire above the substrate, the second multi-layered graphene wire formed wider than the first multi-layered graphene wire and including a multi-layered graphene layer in an edge portion of which the impurity is selectively doped,

a lower-layer contact connected to the undersurface side of the first multi-layered graphene wire, and

an upper-layer contact connected to the upper surface side of the second multi-layered graphene wire; and

wherein each of the first and second multi-layered graphene wires includes a sequentially laminated catalytic underlying layer, catalytic metal layer and the multi-layered graphene layer from the lower-layer side.

2. The device according to claim 1 , wherein the impurity is one of Br, I, F and Cl.

3. The device according to claim 1 , wherein the lower-layer contact is connected to the semiconductor element via a wire on the lower-layer side of the multi-layered graphene wire and the upper-layer contact is connected to a wire on the upper-layer side of the multi-layered graphene wire.

4. The device according to claim 1 , wherein the first multi-layered graphene wire is arranged in a memory cell region and the second multi-layered graphene wire is arranged in a peripheral circuit region.