Flexible interrupt generation mechanism
View Patent ↗In a testing device, a method for implementing efficient interrupt routing. The method includes receiving an interrupt from a plurality of interrupt causes, consulting an interrupt routing table to determine an output interrupt vector, and forwarding the output interrupt vector to one or more of a plurality of different CPUs in accordance with the interrupt routing table.
1. In a testing device, a method for implementing efficient interrupt routing, comprising:
receiving an interrupt from a plurality of interrupt causes; and
consulting an interrupt routing table to determine an output interrupt vector;
forwarding the output interrupt vector to one or more of a plurality of different CPUs in accordance with the interrupt routing table.
2. The method of claim 1 , wherein the testing device comprises a plurality of pin electronics modules.
3. The method of claim 1 , wherein the testing device comprises a plurality of pin electronics modules and each of the pin electronics modules includes a plurality of bridge components and a plurality of CPUs.
4. The method of claim 1 , wherein the testing device comprises a plurality of pin electronics modules coupled together via a high-speed bus, wherein said high-speed bus supports data transfers of at least 400 million bits per second.
5. The method of claim 1 , wherein the testing device comprises a plurality of pin electronics modules having a plurality of bridge components, wherein each bridge component comprises two half bridge components.
6. The method of claim 1 , wherein the testing device comprises a plurality of pin electronics modules, and wherein each of the pin electronics modules is configured to couple to a plurality of devices under test.
7. The method of claim 1 , wherein the testing device comprises a plurality of pin electronics modules, and wherein the pin electronics modules can be configured to support different combined resource modes of operation.
8. The method of claim 1 , wherein the testing device comprises a plurality of pin electronics modules, and wherein the pin electronics modules can be configured to support different combined resource modes of operation including the use of a plurality of CPUs and a plurality of bridge components.
9. A non-transitory computer readable memory having computer readable code which when executed by a computer system causes the computer system to implement a method for implementing efficient interrupt routing, comprising:
receiving an interrupt from a plurality of interrupt causes;
consulting an interrupt routing table to determine an output interrupt vector; and
forwarding the output interrupt vector to one or more of a plurality of different CPUs in accordance with the interrupt routing table.
10. The computer readable memory of claim 9 , wherein the computer system comprises a plurality of pin electronics modules.
11. The computer readable memory of claim 9 , wherein the computer system comprises a plurality of pin electronics modules and each of the pin electronics modules includes a plurality of bridge components and a plurality of CPUs.
12. The computer readable memory of claim 9 , wherein the computer system comprises a plurality of pin electronics modules coupled together via a Link Bus 2 interface.
13. The computer readable memory of claim 9 , wherein the computer system comprises a plurality of pin electronics modules having a plurality of bridge components, wherein each bridge component comprises two half bridge components.
14. The computer readable memory of claim 9 , wherein the computer system comprises a plurality of pin electronics modules, and wherein each of the pin electronics modules is configured to couple to a plurality of devices under test.
15. The computer readable memory of claim 9 , wherein the computer system comprises a plurality of pin electronics modules, and wherein the pin electronics modules can be configured to support different combined resource modes of operation.
16. In a testing device, a method for implementing efficient interrupt routing, comprising:
receiving an interrupt from a plurality of interrupt causes; and
consulting an interrupt routing table to determine an output interrupt vector;
forwarding the output interrupt vector to one or more of a plurality of different CPUs in accordance with the interrupt routing table,
wherein the testing device comprises a plurality of pin electronics modules and each of the pin electronics modules includes a plurality of bridge components and a plurality of CPUs.
17. The method of claim 16 , wherein the testing device pin electronics modules are coupled together via a high-speed bus, wherein said high-speed bus supports data transfers of at least 400 million bits per second.
18. The method of claim 16 , wherein the testing device comprises a plurality of pin electronics modules having a plurality of bridge components, wherein each bridge component comprises two half bridge components.
19. The method of claim 16 , wherein each of the pin electronics modules is configured to couple to a plurality of devices under test.
20. The method of claim 16 , wherein the pin electronics modules can be configured to support different combined resource modes of operation.