IP Library Granted Patent US 9,563,565
Granted Patent B2
US 9,563,565 · App. 13/967,250 · Granted Feb 7, 2017

Apparatuses and methods for providing data from a buffer

Inventors: Graziano Mirichigni (Vimercate, IT); Luca Porzio (Volla, IT); Erminio Di Martino (Quarto, IT); Giacomo Bernardi (Marcianise, IT); Domenico Monteleone (Caserta, IT); Stefano Zanardi (Seriate, IT)
Assignee: Micron Technology, Inc.
G06F12/0891
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Quick Facts
Patent No.
US 9,563,565
App. No.
13/967,250
Granted
Feb 7, 2017
Kind
B2
Abstract

Apparatuses and methods for providing data from a buffer are disclosed herein. An example apparatus may include an array, a buffer, and a memory control unit. The buffer may be coupled to the array and configured to store data. The data may include data intended to be stored in the storage area. The memory control unit may be coupled to the array and the buffer. The memory control unit may be configured to cause the buffer to store the data responsive, at least in part, to a write command and may further be configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.

Claims (58)

1. An apparatus, comprising:

a memory array including an area designated as a storage area for persistent data storage;

a buffer coupled to the memory array and configured to store data to the memory array, the buffer including a plurality of cache lines, each cache line of the plurality of cache lines configured to store data, wherein each of the cache lines of the plurality of cache lines includes a usage field configured to store information indicating whether the cache line includes data to be stored in the storage area of the memory array; and

a memory control unit coupled to the array and the buffer, the memory control unit configured to cause the buffer to store the data responsive, at least in part, to a write command, the memory control unit further configured to identify data stored in the buffer as data to be stored in the storage area based on the information stored in the usage field and further configured to cause the identified data to be stored in the storage area of the array responsive, at least in part, to a flush command, the memory control unit further configured to interrupt the flush command to prepare for a read command or the write command and resume the flush command once the read command or the write command is performed.

2. The apparatus of claim 1 , further comprising:

a host coupled to the memory control unit and configured to provide the flush command.

3. The apparatus of claim 1 , wherein the storage area comprises non-volatile memory.

4. The apparatus of claim 1 , wherein the memory control unit is further configured to cause data stored in the buffer not identified to be stored in the storage area to be stored in the memory array after causing data identified as data to be stored in the storage area to be stored in the storage area of the memory array.

5. The apparatus of claim 1 , wherein each of the plurality of cache lines comprise:

an address field configured to store an address; and

a usage field configured to store information indicating whether the cache line is in use.

6. The apparatus of claim 1 , wherein the memory control unit is further configured to adjust at least one of the size or offset of the storage area of the array.

7. An apparatus, comprising:

an; and

a buffer coupled to the array and comprising:

a plurality of cache lines, each of the plurality of cache lines including a field configured to indicate whether the cache line is in use and further configured to indicate data for storage to a persistent storage area of the array;

a buffer control unit configured to provide data from a first number of cache lines of the plurality of cache lines in use to the array responsive, at least in part, to a second number of cache lines of the plurality of cache lines being in use; and

a memory control unit coupled to the buffer and configured to cause the buffer control unit to selectively provide data from cache lines of the plurality of cache lines having the field indicate data for storage to the persistent storage area of the array responsive, at least in part, to receipt of a flush command, the memory control unit further configured to interrupt the flush command to prepare for a read or write command and resume the flush command once the read or write command is performed.

8. The apparatus of claim 7 , wherein the apparatus is included in a memory.

9. The apparatus of claim 7 , wherein the first number of cache lines is smaller than the second number of cache lines.

10. An apparatus, comprising:

an array having a non-volatile storage area;

a buffer coupled to the array and comprising a plurality of cache lines, each of the cache lines of the plurality of cache lines including an indicator identifying if data stored by the respective cache line is to be provided to the non-volatile storage area; and

a memory control unit coupled to the buffer and configured to cause the cache lines of the plurality of cache lines having the indicator identifying the data stored by the respective cache line as data to be provided to the non-volatile storage area responsive, at least in part, to a flush command before any data stored by the plurality of cache lines not identified as being provided to the non-volatile storage area, the memory control unit further configured to interrupt the flush command to prepare for a read or write command and resume the flush command once the read or write command is performed.

11. The apparatus of claim 10 , wherein each of the cache lines of the plurality of cache lines includes a usage field configured to include the indicator for data stored by the respective cache line.

12. A method, comprising:

receiving a command and an address;

selecting a cache line of a plurality of cache lines based, at least in part, on the address;

storing data in the selected cache line and further storing an address associated with the data;

if a number of cache lines in use of the plurality of cache lines satisfies a threshold, performing a transfer operation to store the data in the array;

responsive to a flush command, identifying data stored by the plurality of cache lines to be stored in a non-volatile storage area of the array based on addresses associated with the data that are located in the non-volatile storage area and storing the data stored by the plurality of cache lines to be stored in the non-volatile storage area of the array in the storage area at a different time than data stored by the plurality of cache lines not to be stored in the non-volatile storage area of the array;

interrupting the flush command to prepare for a read command or the write command;

and resuming the flush command once the read command or write command is performed.

13. The method claim 12 , wherein selecting a cache line of a plurality of cache lines based, at least in part, on the address comprises:

determining whether any of a plurality of cache lines are associated with the address;

if a cache line of the plurality of cache lines is associated with the address, selecting the associated cache line; and

if no cache line of the plurality of cache lines is associated with the address, selecting a cache line of the plurality of cache lines not in use.

14. The method of claim 13 , wherein determining whether any of a plurality of cache lines are associated with the address comprises determining whether the address matches an address stored in a respective address field of a cache line of the plurality of cache lines.

15. The method of claim 12 , wherein storing the data in the selected cache line comprises:

storing the data in a data field of the selected cache line and updating a usage field.

16. The method of claim 12 , wherein performing a transfer operation to store the data in an array at the address is based, at least in part, on information stored in an age field of the selected cache line.

17. A method, comprising:

receiving a write command and an address on a first bus;

receiving write data on a second bus;

storing the write data in a cache line of a buffer including storing information indicative of whether the write data is to be stored in a storage area of an array;

identifying write data stored in the buffer indicated to be stored in the storage area of the array and storing the write data indicated to be stored in the storage area to the storage area of the array responsive, at least in part, to a flush command;

interrupting the flush command to prepare for a read command or the write command;

and resuming the flush command once the read command or write command is performed.

18. The method of claim 17 , further comprising:

storing data in the buffer not indicated to be stored in the storage area to the array after the write data indicated to be stored in the storage area is stored.

19. The method of claim 17 , wherein storing the write data in a cache line of a buffer comprises:

selecting a cache line based, at least in part, on the address;

receiving data from the array associated with the address;

storing the data received from the array in the selected cache line; and

storing the write data in the selected cache line.

20. The method of claim 17 , further comprising:

receiving a read flag status register command; and

providing a state of a flush bit indicating whether the buffer includes write data not yet stored in the array responsive, at least in part, to the read flag status register command.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 14, 2013
From: MIRICHIGNI, GRAZIANO; PORZIO, LUCA; DI MARTINO, ERMINIO; BERNARDI, GIACOMO; MONTELEONE, DOMENICO; ZANARDI, STEFANO
To: MICRON TECHNOLOGY, INC.
Reel/Frame 031011/0861 →
Continuity (1)
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