IP Library Granted Patent US 8,652,899
Granted Patent B2
US 8,652,899 · App. 13/967,338 · Granted Feb 18, 2014

Method of fabricating pixel structure

Inventors: Chien-Chih Lee (Hsin-Chu, TW); Pei-Yi Shen (Hsin-Chu, TW); Ching-Yang Cheng (Hsin-Chu, TW); Shu-Ming Huang (Hsin-Chu, TW)
Assignee: AU Optronics Corp.
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Quick Facts
Patent No.
US 8,652,899
App. No.
13/967,338
Granted
Feb 18, 2014
Kind
B2
Abstract

The present invention provides a pixel structure including a substrate, a patterned electrode disposed on the substrate, a first insulating layer disposed on the patterned electrode, a common electrode disposed on the first insulating layer, a second insulating layer disposed on the common electrode, and a drain disposed on the second insulating layer. The first insulating layer has a first through hole, and the second insulating layer has a second through hole. The drain includes a first portion electrically connected to the patterned electrode via the first through hole and the second through hole, and a second portion extending onto the common electrode. The common electrode is coupled with the patterned electrode to form a first storage capacitor and is coupled with the second portion to form a second storage capacitor.

Claims (18)

1. A method of fabricating a pixel structure, comprising:

providing a substrate;

forming a gate and a patterned electrode on the substrate;

forming a first insulating layer on the gate, the patterned electrode and the substrate, and forming a common electrode on the first insulating layer;

forming a second insulating layer on the first insulating layer and the common electrode, and forming a semiconductor channel layer on the second insulating layer;

forming a second through hole in the second insulating layer, and forming a first through hole in the first insulating layer via the second through hole to expose a part of the patterned electrode;

forming a source and a drain on the semiconductor channel layer and the second insulating layer, and the drain comprising a first portion and a second portion, the first portion of the drain being connected to the second portion of the drain, the first portion of the drain being electrically connected to the patterned electrode via the first through hole and the second through hole, the second portion of the drain extending onto the common electrode, wherein the patterned electrode and the common electrode partially overlap and are coupled with each other to form a first storage capacitor, and the second portion of the drain and the common electrode partially overlap and are coupled with each other to form a second storage capacitor;

forming a passivation layer on the second insulating layer, the semiconductor channel layer, the source, and the drain;

forming a third through hole in the passivation layer to expose a part of the drain; and

forming a pixel electrode, and the pixel electrode being electrically connected to the drain via the third through hole.

2. The method of fabricating the pixel structure according to claim 1 , wherein the step of forming the gate and the patterned electrode comprises:

forming a metal layer; and

patterning the metal layer to form the gate and the patterned electrode.

3. The method of fabricating the pixel structure according to claim 1 , wherein the step of forming the first through hole and the step of forming the second through are performed by a same etching process.

4. The method of fabricating the pixel structure according to claim 1 , further comprising forming an organic layer on the passivation layer between the step of forming the passivation layer and the step of forming the third through hole.

5. The method of fabricating the pixel structure according to claim 4 , further comprising forming a fourth through hole in the organic layer corresponding to the third through hole between the step of forming the organic layer and the step of forming the third through hole.

6. The method of fabricating the pixel structure according to claim 1 , wherein a material of forming the common electrode is metal.

7. The method of fabricating the pixel structure according to claim 1 , further comprising forming a heavily doped semiconductor layer on the semiconductor channel layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 24, 2025
From: AUO CORPORATION
To: NEOLAYER LLC
Reel/Frame 072266/0941 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 14, 2013
From: LEE, CHIEN-CHIH; SHEN, PEI-YI; CHENG, CHING-YANG; HUANG, SHU-MING
To: AU OPTRONICS CORP.
Reel/Frame 031012/0611 →
Priority Claims (1)
TW 100124773 A · Jul 13, 2011 · national
Continuity (2)
Division 13461798 · May 2, 2012
Related Publication 20130323889A1 · Dec 5, 2013